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公开(公告)号：US09966320B2
公开(公告)日：2018-05-08
申请号：US15270145
申请日：2016-09-20
Applicant: RAYTHEON COMPANY
Inventor： Roland W. Gooch , Buu Q. Diep , Adam M. Kennedy , Stephen H. Black , Thomas A. Kocian
IPC: H01L23/48 , H01L23/02 , H01L23/10 , H01L23/498 , H01L21/768 , B81B7/00 , H01L23/26 , H01L27/146 , B81C1/00 , H01L21/52
CPC classification number: H01L23/10 , B81B7/0038 , B81B2201/0207 , B81C1/00269 , B81C2203/035 , H01L21/52 , H01L21/76841 , H01L23/26 , H01L23/49866 , H01L27/14618 , H01L27/14634 , H01L27/14636 , H01L27/14683 , H01L27/1469 , H01L2224/16 , H01L2924/0002 , H01L2924/00
Abstract: An electronic device and methods of manufacture thereof. One or more methods may include providing a lid wafer having a cavity and a surface surrounding the cavity and a device wafer having a detector device and a reference device. In certain examples, a solder barrier layer of titanium material may be deposited onto the surface of the lid wafer. The solder barrier layer of titanium material may further be activated to function as a getter. In various examples, the lid wafer and the device wafer may be bonded together using solder, and the solder barrier layer of titanium material may prevent the solder from contacting the surface of the lid wafer.
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公开(公告)号：US09865519B2
公开(公告)日：2018-01-09
申请号：US15402329
申请日：2017-01-10
Applicant: RAYTHEON COMPANY
Inventor： Stephen H. Black , Adam M. Kennedy
CPC classification number: H01L23/26 , H01L21/3221 , H01L21/3225 , H01L21/4817 , H01L21/54 , H01L23/041 , H01L23/10
Abstract: A system and method for forming a wafer level package. In one example, a substrate used in the wafer level package includes a surface defined by a wafer level package (WLP) region and an external region, and a layer of getter material is disposed on at least a portion of the external region. According to one embodiment, the external region comprises a saw-to-reveal (STR) region of the wafer.
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公开(公告)号：US09570321B1
公开(公告)日：2017-02-14
申请号：US14887544
申请日：2015-10-20
Applicant: RAYTHEON COMPANY
Inventor： Stephen H. Black , Adam M. Kennedy
IPC: H01L21/322 , H01L23/26 , H01L23/544
CPC classification number: H01L23/26 , H01L21/3221 , H01L21/3225 , H01L21/4817 , H01L21/54 , H01L23/041 , H01L23/10
Abstract: A system and method for forming a wafer level package. In one example, a substrate used in the wafer level package includes a surface defined by a wafer level package (WLP) region and an external region, and a layer of getter material is disposed on at least a portion of the external region. According to one embodiment, the external region comprises a saw-to-reveal (STR) region of the wafer.
Abstract translation: 一种用于形成晶片级封装的系统和方法。 在一个示例中，用于晶片级封装的衬底包括由晶片级封装（WLP）区域和外部区域限定的表面，并且吸收材料层设置在外部区域的至少一部分上。 根据一个实施例，外部区域包括晶片的锯切（STR）区域。
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14.发明授权公开(公告)号：US09174836B2
公开(公告)日：2015-11-03
申请号：US14456156
申请日：2014-08-11
Applicant: Raytheon Company
Inventor： Roland Gooch , Buu Diep , Thomas Allan Kocian , Stephen H. Black , Adam M. Kennedy
IPC: H01L23/12 , B81B7/00 , B81C1/00 , H01L23/053 , H01L23/00
CPC classification number: B81B7/0041 , B81B7/007 , B81C1/00269 , B81C2203/019 , H01L23/053 , H01L24/27 , H01L24/29 , H01L24/83 , H01L2224/27444 , H01L2224/27462 , H01L2224/27464 , H01L2224/29011 , H01L2224/291 , H01L2224/83001 , H01L2224/83007 , H01L2224/83139 , H01L2224/8314 , H01L2224/83141 , H01L2224/83192 , H01L2924/1461 , H01L2924/163 , H01L2924/00014 , H01L2924/014
Abstract: A method of forming a wafer level packaged circuit device includes forming a device wafer, the device wafer including a first group of one or more material layers left remaining in a first region of a substrate of the device wafer; and forming a cap wafer configured to be attached to the device wafer, the cap wafer including a second group of one or more material layers left remaining in a second region of a substrate of the cap wafer; wherein a combined thickness of the first and second groups of one or more material layers defines an integrated bond gap control structure upon bonding of the device wafer and the cap wafer.
Abstract translation: 一种形成晶片级封装电路器件的方法包括形成器件晶片，器件晶片包括残留在器件晶片的衬底的第一区域中的第一组一个或多个材料层; 以及形成被配置为附接到所述器件晶片的盖晶片，所述盖晶片包括留在所述盖晶片的衬底的第二区域中的第二组一个或多个材料层; 其中一个或多个材料层的所述第一和第二组的组合厚度在所述器件晶片和所述盖晶片接合时限定了整合的接合间隙控制结构。
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公开(公告)号：US20150162479A1
公开(公告)日：2015-06-11
申请号：US14100048
申请日：2013-12-09
Applicant: Raytheon Company
Inventor： Roland Gooch , Thomas Allan Kocian , Buu Diep , Adam M. Kennedy , Stephen H. Black
IPC: H01L31/18 , H01L31/0232
CPC classification number: H01L31/18 , B81C1/00373 , B81C2201/0188 , H01L31/02327
Abstract: A method for forming a coating of material on selected portions of a surface of a substrate having a plurality of cavities, each cavity having outer, peripheral sidewalls extending outwardly from the surface. The method includes: providing a structure having a release agent thereon; contacting top surface of the wafer with the release agent to transfer portions of the release agent to the top surface of the wafer while bottom portions of the cavities remain spaced from the release agent to produce an intermediate structure; the release agent disposed on the top surface of the wafer and with the bottom portions of the cavities void of the release agent; exposing the intermediate structure to the material to blanket coat the material on both the release agent and the bottom portions of the cavities; and selectively removing the release agent together with the coating material while leaving the coating material on the bottom portions of the cavities.
Abstract translation: 一种用于在具有多个空腔的基板的表面的选定部分上形成材料涂层的方法，每个空腔具有从表面向外延伸的外部周边侧壁。 该方法包括：提供其上具有脱模剂的结构; 使所述晶片的顶表面与所述脱模剂接触以将所述脱模剂的部分转移到所述晶片的顶表面，同时所述空腔的底部保持与所述脱模剂间隔开以产生中间结构; 所述脱模剂设置在所述晶片的顶表面上，并且所述空腔的底部部分脱离所述脱模剂; 将所述中间结构暴露于所述材料以在所述空腔的所述脱模剂和所述底部两者上均匀地涂覆所述材料; 并且与涂料一起选择性地除去脱模剂，同时将涂料留在空腔的底部。
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Patent Agency Ranking
公开(公告)号：US10315918B2
公开(公告)日：2019-06-11
申请号：US15227181
申请日：2016-08-03
Applicant: RAYTHEON COMPANY
Inventor： Roland W. Gooch , Buu Q. Diep , Stephen H. Black , Thomas A. Kocian , Adam M. Kennedy
Abstract: Methods for reducing wafer bow induced by an anti-reflective coating of a cap wafer are provided. The method may utilize a shadow mask having at least one opening therein that is positioned opposite recessed regions in a cap wafer. The method may further include depositing at least one layer of an anti-reflective coating material through the shadow mask onto a planar side of a cap wafer to provide a discontinuous coating on the planar side.
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17.发明授权Method and apparatus for inhibiting diversion of devices using an embedded accelerometer 有权使用嵌入式加速度计抑制装置转向的方法和装置公开(公告)号：US09407820B2
公开(公告)日：2016-08-02
申请号：US13768505
申请日：2013-02-15
Applicant: RAYTHEON COMPANY
Inventor： Stephen H. Black , Paolo Masini
CPC classification number: H04N5/23241 , G01J1/0228 , G01J2001/0257 , G01P15/00 , G01P15/0891 , H04N5/33
Abstract: According to one aspect, embodiments herein provide a sensing device comprising an accelerometer configured to monitor acceleration of the sensing device and provide acceleration information including a value of the acceleration of the sensing device, and an Integrated Circuit (IC) coupled to the accelerometer, the IC configured to receive the acceleration information from the accelerometer and render the sensing device permanently inoperable in response to the value of the acceleration of the sensing device exceeding a threshold indicative of a military application of the sensing device.
Abstract translation: 根据一个方面，本文的实施例提供一种感测装置，其包括加速度计，该加速度计被配置为监测感测装置的加速度并提供包括感测装置的加速度值的加速度信息，以及耦合到加速度计的集成电路（IC） IC被配置为从加速度计接收加速度信息并且使得感测装置响应于感测装置的加速度的值超过表示感测装置的军事应用的阈值而永久地不可操作。
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公开(公告)号：US09105800B2
公开(公告)日：2015-08-11
申请号：US14100048
申请日：2013-12-09
Applicant: Raytheon Company
Inventor： Roland Gooch , Thomas Allan Kocian , Buu Diep , Adam M. Kennedy , Stephen H. Black
IPC: H01L31/18 , H01L31/0232
CPC classification number: H01L31/18 , B81C1/00373 , B81C2201/0188 , H01L31/02327
Abstract: A method for forming a coating of material on selected portions of a surface of a substrate having a plurality of cavities, each cavity having outer, peripheral sidewalls extending outwardly from the surface. The method includes: providing a structure having a release agent thereon; contacting top surface of the wafer with the release agent to transfer portions of the release agent to the top surface of the wafer while bottom portions of the cavities remain spaced from the release agent to produce an intermediate structure; the release agent disposed on the top surface of the wafer and with the bottom portions of the cavities void of the release agent; exposing the intermediate structure to the material to blanket coat the material on both the release agent and the bottom portions of the cavities; and selectively removing the release agent together with the coating material while leaving the coating material on the bottom portions of the cavities.
Abstract translation: 一种用于在具有多个空腔的基板的表面的选定部分上形成材料涂层的方法，每个空腔具有从表面向外延伸的外部周边侧壁。 该方法包括：提供其上具有脱模剂的结构; 使所述晶片的顶表面与所述脱模剂接触以将所述脱模剂的部分转移到所述晶片的顶表面，同时所述空腔的底部保持与所述脱模剂间隔开以产生中间结构; 所述脱模剂设置在所述晶片的顶表面上，并且所述空腔的底部部分脱离所述脱模剂; 将所述中间结构暴露于所述材料以在所述空腔的所述脱模剂和所述底部两者上均匀地涂覆所述材料; 并且与涂料一起选择性地除去脱模剂，同时将涂料留在空腔的底部。
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公开(公告)号：US20140346643A1
公开(公告)日：2014-11-27
申请号：US14456156
申请日：2014-08-11
Applicant: Raytheon Company
Inventor： Roland Gooch , Buu Diep , Thomas Allan Kocian , Stephen H. Black , Adam M. Kennedy
IPC: B81B7/00
CPC classification number: B81B7/0041 , B81B7/007 , B81C1/00269 , B81C2203/019 , H01L23/053 , H01L24/27 , H01L24/29 , H01L24/83 , H01L2224/27444 , H01L2224/27462 , H01L2224/27464 , H01L2224/29011 , H01L2224/291 , H01L2224/83001 , H01L2224/83007 , H01L2224/83139 , H01L2224/8314 , H01L2224/83141 , H01L2224/83192 , H01L2924/1461 , H01L2924/163 , H01L2924/00014 , H01L2924/014
Abstract: A method of forming a wafer level packaged circuit device includes forming a device wafer, the device wafer including a first group of one or more material layers left remaining in a first region of a substrate of the device wafer; and forming a cap wafer configured to be attached to the device wafer, the cap wafer including a second group of one or more material layers left remaining in a second region of a substrate of the cap wafer; wherein a combined thickness of the first and second groups of one or more material layers defines an integrated bond gap control structure upon bonding of the device wafer and the cap wafer.
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20.发明申请METHOD OF STRESS RELIEF IN ANTI-REFLECTIVE COATED CAP WAFERS FOR WAFER LEVEL PACKAGED INFRARED FOCAL PLANE ARRAYS 有权用于水平包装的红外焦平面阵列的抗反射涂层盖子中的应力消除方法公开(公告)号：US20140053966A1
公开(公告)日：2014-02-27
申请号：US13688714
申请日：2012-11-29
Applicant: RAYTHEON COMPANY
Inventor： Roland W. Gooch , Buu Q. Diep , Stephen H. Black , Thomas A. Kocian , Adam M. Kennedy
IPC: B05D5/06
CPC classification number: B81C1/00325 , B05D5/061 , B81B7/0067 , B81B2201/0207 , B81C2203/0118
Abstract: Methods for reducing wafer bow induced by an anti-reflective coating of a cap wafer are provided. The method may utilize a shadow mask having at least one opening therein that is positioned opposite recessed regions in a cap wafer. The method may further include depositing at least one layer of an anti-reflective coating material through the shadow mask onto a planar side of a cap wafer to provide a discontinuous coating on the planar side.
Abstract translation: 提供了通过盖晶片的抗反射涂层引起的减少晶片弓的方法。 该方法可以利用其中具有至少一个开口的荫罩，其位于帽晶片中的相对凹陷区域。 该方法还可以包括将至少一层抗反射涂层材料通过荫罩沉积到盖晶片的平面侧上，以在平面侧上提供不连续的涂层。
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