Abstract:
A semiconductor device includes a line; a source structure on the line; a stack structure on the source structure; a first slit structure penetrating the stack structure; a second slit structure penetrating the stack structure; and a contact plug adjacent to the first slit structure in a first direction. The first slit structure and the second slit structure may be spaced apart from each other by a first distance in a second direction that is perpendicular to the first direction. The contact plug penetrates the source structure, the contact plug being electrically connected to the lower line. The first slit structure and the contact plug may be spaced apart from each other by a second distance in the first direction, and the second distance may be longer than the first distance.
Abstract:
A chip stack embedded package includes a first dielectric layer having a multistep cavity therein, a first plurality of semiconductor chips disposed in a first level of the multistep cavity, a second plurality of semiconductor chips disposed in a second level of the multistep cavity, and a second dielectric layer filling the multistep cavity to cover the first and second pluralities of semiconductor chips.
Abstract:
An embedded image sensor package includes a core layer having a cavity therein, an image sensor chip disposed in the cavity and having a top surface on which a light receiver and connection members are disposed, a first insulation layer disposed on a top surface of the core layer and the top surface of the image sensor chip and having an opening that defines a light receiving area including the light receiver, a protection layer disposed between the light receiver and the first insulation layer to surround the light receiver, and a light transmission layer disposed on the light receiver. The protection layer is disposed along edges of the light receiving area. Related methods are also provided.
Abstract:
Embedded packages are provided. The embedded package includes a chip attached to a first surface of a core layer, a plurality of bumps on a surface of the chip opposite to the core layer, and a first insulation layer surrounding the core layer, the chip and the plurality of bumps. The first insulation layer has a trench disposed in a portion of the first insulation layer to expose the plurality of bumps.