公开(公告)号：US12260119B2

公开(公告)日：2025-03-25

申请号：US18081688

申请日：2022-12-15

Applicant: SK hynix Inc.

Inventor： Hyun Woo Bae ,  Sang Yong Lee

IPC: G06F3/06

Abstract: A memory system according to the present technology includes a nonvolatile memory area, a buffer memory area temporarily storing data, and a plurality of cores configured to store, in the nonvolatile memory area, the data stored in the buffer memory area in response to a sudden power off, each of the plurality of cores outputting an interrupt signal indicating that the sudden power off is sensed.

公开(公告)号：US11610915B2

公开(公告)日：2023-03-21

申请号：US17243270

申请日：2021-04-28

Applicant: SK hynix Inc.

Inventor： Sang Yong Lee ,  Sang Min Kim ,  Jung Ryul Ahn ,  Sang Hyun Oh ,  Seung Bum Cha ,  Kang Sik Choi

IPC: H01L27/11582 ,  H01L25/065 ,  H01L27/06 ,  H01L27/11556

Abstract: A semiconductor device includes: a first stack structure; a second stack structure adjacent to the first stack structure in a first direction; a first insulating layer including protrusion parts protruding in a second direction intersecting the first direction and including a concave part defined between the protrusion parts; and a second insulating layer located between the first stack structure and the second stack structure, the second insulating layer inserted into the concave part and the second insulating layer in contact with at least one protrusion part among the protrusion parts.

公开(公告)号：US09209146B2

公开(公告)日：2015-12-08

申请号：US14532393

申请日：2014-11-04

Applicant: SK hynix Inc.

Inventor： Seung Jee Kim ,  Qwan Ho Chung ,  Jong Hyun Nam ,  Si Han Kim ,  Sang Yong Lee ,  Seong Cheol Shin

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L21/768 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L24/11 ,  H01L21/56 ,  H01L21/768 ,  H01L23/3121 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/19 ,  H01L24/83 ,  H01L2224/02333 ,  H01L2224/02351 ,  H01L2224/02372 ,  H01L2224/02379 ,  H01L2224/03334 ,  H01L2224/0346 ,  H01L2224/03472 ,  H01L2224/03474 ,  H01L2224/03903 ,  H01L2224/03906 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05017 ,  H01L2224/05026 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/11334 ,  H01L2224/11602 ,  H01L2224/1184 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/211 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00

Abstract: An electronic device package includes a bump having a post disposed on a contact portion of a semiconductor chip and an enlarged portion laterally protruded from an upper portion of the post; an interconnection portion having a locking portion that substantially surrounds the enlarged portion and an upper sidewall of the post; and a dielectric layer substantially surrounding the bump and the locking portion to separate the interconnection portion from the semiconductor chip.

Abstract translation: 电子器件封装包括具有设置在半导体芯片的接触部分上的柱和从柱的上部侧向突出的扩大部分的凸块; 互连部分，其具有基本上围绕所述柱的扩大部分和上侧壁的锁定部分; 以及基本上围绕所述凸起和所述锁定部分的绝缘层，以将所述互连部分与所述半导体芯片分离。

公开(公告)号：US09985002B2

公开(公告)日：2018-05-29

申请号：US15630084

申请日：2017-06-22

Applicant: SK hynix Inc.

Inventor： Sang Yong Lee

IPC: H05K1/16 ,  H01L23/48 ,  H01L25/065 ,  H01L23/31 ,  H01L23/00 ,  H01L23/13 ,  H01L25/00 ,  H01L23/538 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5384 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/50 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/16237 ,  H01L2224/29007 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73103 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/8114 ,  H01L2224/81385 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2224/83 ,  H01L2224/8385 ,  H01L2224/9211 ,  H01L2224/92242 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06562 ,  H01L2924/1435 ,  H01L2924/15156 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/81

Abstract: The stack package includes a substrate body layer having a top surface and a bottom surface, first circuit patterns disposed on the bottom surface of the substrate body layer, second circuit patterns disposed on the top surface of the substrate body layer, a first semiconductor chip including first bumps, and a second semiconductor chip including second bumps. The first bumps extend through the substrate body layer to be electrically coupled to the first circuit patterns, and the second bumps extend past sidewalls of the first semiconductor chip to be electrically coupled to the second circuit patterns. The second semiconductor chip is stacked on the first semiconductor chip.

公开(公告)号：US11973022B2

公开(公告)日：2024-04-30

申请号：US16917410

申请日：2020-06-30

Applicant: SK hynix Inc.

Inventor： Sang Yong Lee ,  Sae Jun Kwon ,  Sang Min Kim ,  Jin Taek Park ,  Sang Hyun Oh

IPC: H01L23/52 ,  H01L23/48 ,  H01L23/522 ,  H01L27/11582 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H01L23/5226 ,  H01L23/481 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A semiconductor device includes a line; a source structure on the line; a stack structure on the source structure; a first slit structure penetrating the stack structure; a second slit structure penetrating the stack structure; and a contact plug adjacent to the first slit structure in a first direction. The first slit structure and the second slit structure may be spaced apart from each other by a first distance in a second direction that is perpendicular to the first direction. The contact plug penetrates the source structure, the contact plug being electrically connected to the lower line. The first slit structure and the contact plug may be spaced apart from each other by a second distance in the first direction, and the second distance may be longer than the first distance.

公开(公告)号：US11024647B2

公开(公告)日：2021-06-01

申请号：US16903113

申请日：2020-06-16

Applicant: SK hynix Inc.

Inventor： Sang Yong Lee ,  Sang Min Kim ,  Jung Ryul Ahn ,  Sang Hyun Oh ,  Seung Bum Cha ,  Kang Sik Choi

IPC: H01L27/11582 ,  H01L25/065 ,  H01L27/06 ,  H01L27/11556

Abstract: A semiconductor device includes: a first stack structure; a second stack structure adjacent to the first stack structure in a first direction; a first insulating layer including protrusion parts protruding in a second direction intersecting the first direction and including a concave part defined between the protrusion parts; and a second insulating layer located between the first stack structure and the second stack structure, the second insulating layer inserted into the concave part and the second insulating layer in contact with at least one protrusion part among the protrusion parts.

公开(公告)号：US10727247B2

公开(公告)日：2020-07-28

申请号：US16180966

申请日：2018-11-05

Applicant: SK hynix Inc.

Inventor： Sang Yong Lee ,  Sang Min Kim ,  Jung Ryul Ahn ,  Sang Hyun Oh ,  Seung Bum Cha ,  Kang Sik Choi

IPC: H01L27/11582 ,  H01L25/065 ,  H01L27/06 ,  H01L27/11556

Abstract: A semiconductor device includes: a first stack structure; a second stack structure adjacent to the first stack structure in a first direction; a first insulating layer including protrusion parts protruding in a second direction intersecting the first direction and including a concave part defined between the protrusion parts; and a second insulating layer located between the first stack structure and the second stack structure, the second insulating layer inserted into the concave part and the second insulating layer in contact with at least one protrusion part among the protrusion parts.

公开(公告)号：US09721924B2

公开(公告)日：2017-08-01

申请号：US14483288

申请日：2014-09-11

Applicant: SK hynix Inc.

Inventor： Sang Yong Lee

IPC: H01L23/48 ,  H01L25/065 ,  H01L23/31 ,  H01L23/00 ,  H01L23/13 ,  H01L25/00 ,  H01L23/538 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5384 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/50 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/16237 ,  H01L2224/29007 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73103 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/8114 ,  H01L2224/81385 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2224/83 ,  H01L2224/8385 ,  H01L2224/9211 ,  H01L2224/92242 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06562 ,  H01L2924/1435 ,  H01L2924/15156 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/81

Abstract: The stack package includes a substrate body layer having a top surface and a bottom surface, first circuit patterns disposed on the bottom surface of the substrate body layer, second circuit patterns disposed on the top surface of the substrate body layer, a first semiconductor chip including first bumps, and a second semiconductor chip including second bumps. The first bumps extend through the substrate body layer to be electrically coupled to the first circuit patterns, and the second bumps extend past sidewalls of the first semiconductor chip to be electrically coupled to the second circuit patterns. The second semiconductor chip is stacked on the first semiconductor chip.

公开(公告)号：US09324688B2

公开(公告)日：2016-04-26

申请号：US14273485

申请日：2014-05-08

Applicant: SK HYNIX INC.

Inventor： Ki Jun Sung ,  Seung Jee Kim ,  Jong Hyun Nam ,  Sang Yong Lee ,  Young Geun Yoo

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/03 ,  H05K1/18 ,  H05K3/46 ,  H01L23/538

CPC classification number: H01L25/0652 ,  H01L23/5389 ,  H01L24/09 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L25/03 ,  H01L2224/09134 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/2101 ,  H01L2224/215 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2225/06541 ,  H01L2924/15153 ,  H01L2924/181 ,  H05K1/185 ,  H05K3/4697 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10674 ,  H05K2201/10734 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/01029

Abstract: An embedded package includes a first semiconductor chip embedded in a package substrate, a second semiconductor chip disposed over a first surface of the package substrate, and a group of external connection joints disposed on the first surface of the package substrate and between a sidewall of the second semiconductor chip and an edge of the embedded package. Related memory cards and related electronic systems are also provided.

Abstract translation: 嵌入式封装包括嵌入在封装衬底中的第一半导体芯片，设置在封装衬底的第一表面上的第二半导体芯片和设置在封装衬底的第一表面上以及位于封装衬底的侧壁之间的一组外部连接接头 第二半导体芯片和嵌入式封装的边缘。 还提供了相关的存储卡和相关的电子系统。

公开(公告)号：US09099313B2

公开(公告)日：2015-08-04

申请号：US13846807

申请日：2013-03-18

Applicant: SK hynix Inc.

Inventor： Sang Yong Lee ,  Si Han Kim

IPC: H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L23/538 ,  H05K1/18 ,  H05K3/12 ,  H05K3/18 ,  H05K3/46

CPC classification number: H01L24/03 ,  H01L23/3128 ,  H01L23/498 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/2101 ,  H01L2224/214 ,  H01L2224/24011 ,  H01L2224/24051 ,  H01L2224/24226 ,  H01L2224/24227 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/82101 ,  H01L2224/82102 ,  H01L2224/82104 ,  H01L2224/82106 ,  H01L2224/8385 ,  H01L2224/92 ,  H01L2224/92132 ,  H01L2224/92244 ,  H01L2924/12042 ,  H05K1/185 ,  H05K3/12 ,  H05K3/18 ,  H05K3/4644 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2224/19 ,  H01L2924/014 ,  H01L2924/00

Abstract: An embedded package in which active elements, such as semiconductor chips, are embedded within a package substrate. The semiconductor chips, embedded within a dielectric layer, are coupled with circuit wires to ensure electrical and signal continuity. When connections between the semiconductor chip and the package substrate are performed in different directions, there is a reduction in overall interconnection area, connection reliability is improved, leakage currents are reduced, and higher device yields can be realized.

Abstract translation: 嵌入式封装，其中诸如半导体芯片的有源元件嵌入在封装衬底内。 嵌入在介电层内的半导体芯片与电路线耦合以确保电气和信号的连续性。 当在不同的方向上进行半导体芯片和封装基板之间的连接时，总的互连面积减小，连接可靠性提高，泄漏电流降低，并且可以实现更高的器件产量。