公开(公告)号：US12034047B2

公开(公告)日：2024-07-09

申请号：US18056954

申请日：2022-11-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woo Bin Song ,  Sang Woo Lee ,  Min Hee Cho

IPC: H01L29/51 ,  H01L29/08 ,  H01L29/24 ,  H01L29/267 ,  H01L29/417 ,  H01L29/45 ,  H01L29/786

CPC classification number: H01L29/0847 ,  H01L29/24 ,  H01L29/267 ,  H01L29/41733 ,  H01L29/41775 ,  H01L29/45 ,  H01L29/516 ,  H01L29/517 ,  H01L29/7869

Abstract: Aspects of the present inventive concept provide a semiconductor device capable of enhancing performance and reliability through source/drain engineering in a transistor including an oxide semiconductor layer. The semiconductor device includes a substrate, a metal oxide layer disposed on the substrate, a source/drain pattern being in contact with the metal oxide layer and including a portion protruding from a top surface of the metal oxide layer, a plurality of gate structures disposed on the metal oxide layer with the source/drain pattern interposed therebetween and each including gate spacers and an insulating material layer, the insulating material layer being in contact with the metal oxide layer, and not extending along a top surface of the source/drain pattern, and a contact disposed on the source/drain pattern, the contact being connected to the source/drain pattern.

公开(公告)号：US11903184B2

公开(公告)日：2024-02-13

申请号：US17392488

申请日：2021-08-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung Hwan Lee ,  Yong Seok Kim ,  Il Gweon Kim ,  Hui-Jung Kim ,  Min Hee Cho ,  Jae Ho Hong

IPC: H01L27/108 ,  H01L29/24 ,  H10B12/00 ,  G11C11/402

CPC classification number: H10B12/34 ,  G11C11/4023 ,  H01L29/24

Abstract: A semiconductor memory device in which performance and reliability are improved, and a method for fabricating the same are provided. The semiconductor memory device includes a conductive line extending in a first direction on a substrate, an interlayer insulation film that includes a cell trench extending in a second direction intersecting the first direction, on the substrate, a first gate electrode and a second gate electrode that are spaced apart from each other in the first direction and each extend in the second direction, inside the cell trench, a channel layer that is inside the cell trench and is electrically connected to the conductive line, on the first gate electrode and the second gate electrode, and a gate insulation layer interposed between the first gate electrode and the channel layer, and between the second gate electrode and the channel layer.

公开(公告)号：US20220199625A1

公开(公告)日：2022-06-23

申请号：US17392488

申请日：2021-08-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung Hwan Lee ,  Yong Seok Kim ,  Il Gweon Kim ,  Hui-Jung Kim ,  Min Hee Cho ,  Jae Ho Hong

IPC: H01L27/108 ,  G11C11/402 ,  H01L29/24

Abstract: A semiconductor memory device in which performance and reliability are improved, and a method for fabricating the same are provided. The semiconductor memory device includes a conductive line extending in a first direction on a substrate, an interlayer insulation film that includes a cell trench extending in a second direction intersecting the first direction, on the substrate, a first gate electrode and a second gate electrode that are spaced apart from each other in the first direction and each extend in the second direction, inside the cell trench, a channel layer that is inside the cell trench and is electrically connected to the conductive line, on the first gate electrode and the second gate electrode, and a gate insulation layer interposed between the first gate electrode and the channel layer, and between the second gate electrode and the channel layer.

公开(公告)号：US11018137B2

公开(公告)日：2021-05-25

申请号：US16442769

申请日：2019-06-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Beomyong Hwang ,  Min Hee Cho ,  Hei Seung Kim ,  Mirco Cantoro ,  Hyunmog Park ,  Woo Bin Song ,  Sang Woo Lee

IPC: H01L27/10 ,  G11C11/40 ,  H01L27/108 ,  G11C11/402

Abstract: A semiconductor memory device includes a substrate, a first active pattern on the substrate, a gate electrode intersecting a channel region of the first active pattern, a first insulating layer covering the first active pattern and the gate electrode, a contact penetrating the first insulating layer so as to be electrically connected to a first source/drain region of the first active pattern, and a second active pattern on the first insulating layer. A channel region of the second active pattern vertically overlaps with the contact.

公开(公告)号：US10431680B2

公开(公告)日：2019-10-01

申请号：US15391888

申请日：2016-12-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungsam Lee ,  Junsoo Kim ,  Hyoshin Ahn ,  Satoru Yamada ,  Joohyun Jeon ,  MoonYoung Jeong ,  Chunhyung Chung ,  Min Hee Cho ,  Kyo-Suk Chae ,  Eunae Choi

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/04

Abstract: A semiconductor device including a semiconductor substrate including a trench, the semiconductor substrate having a crystal structure; and an insulating layer covering an inner sidewall of the trench, wherein the inner sidewall of the trench has at least one plane included in a {320} family of planes of the crystal structure or at least one plane similar to the {320} family of planes.

公开(公告)号：US20180108662A1

公开(公告)日：2018-04-19

申请号：US15835071

申请日：2017-12-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min Hee Cho ,  Woo Song Ahn ,  Min Su Choi ,  Satoru Yamada ,  Jun Soo Kim ,  Sung Sam Lee

IPC: H01L27/108 ,  H01L29/51 ,  H01L29/423 ,  H01L49/02 ,  H01L29/06

CPC classification number: H01L27/10823 ,  H01L27/10814 ,  H01L27/10876 ,  H01L28/90 ,  H01L29/0649 ,  H01L29/4236 ,  H01L29/51

Abstract: A semiconductor device includes an active region on a substrate, a device isolation film on the substrate to define the active region, a gate trench including a first portion in the active region and a second portion in the device isolation film, a gate electrode including a first gate embedded in the first portion of the gate trench and a second gate embedded in the second portion of the gate trench, a first gate capping pattern on the first gate and filling the first portion of the gate trench, and a second gate capping pattern on the second gate and filling the second portion of the gate trench, an upper surface of the first gate being higher than an upper surface of the second gate, and the first gate capping pattern and the second gate capping pattern have different structures.

公开(公告)号：US12080791B2

公开(公告)日：2024-09-03

申请号：US17400218

申请日：2021-08-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min Tae Ryu ,  Sang Hoon Uhm ,  Ki Seok Lee ,  Min Su Lee ,  Won Sok Lee ,  Min Hee Cho

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/24 ,  H10B12/00

CPC classification number: H01L29/7813 ,  H01L27/088 ,  H01L29/24 ,  H10B12/30

Abstract: A semiconductor memory device with improved performance by improving interface characteristics while reducing a leakage current, and a method for fabricating the same are provided. The semiconductor memory device includes a conductive line on a substrate, a first interlayer insulating layer exposing the conductive line and defining a channel trench on the substrate, a channel layer extending along a bottom and side surface of the channel trench, a first gate electrode and a second gate electrode spaced apart from each other in the channel trench, a first gate insulating layer between the channel layer and the first gate electrode, and a second gate insulating layer between the channel layer and the second gate electrode. The channel layer includes a first oxide semiconductor layer and a second oxide semiconductor layer sequentially stacked on the conductive line. The first oxide semiconductor layer has a greater crystallinity than the second oxide semiconductor layer.

公开(公告)号：US11887653B2

公开(公告)日：2024-01-30

申请号：US17705915

申请日：2022-03-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minsu Lee ,  Min Tae Ryu ,  Wonsok Lee ,  Min Hee Cho

IPC: G11C11/418 ,  G11C11/408 ,  H10B12/00

CPC classification number: G11C11/4085 ,  G11C11/4087 ,  H10B12/315

Abstract: Disclosed is a memory device including a row decoder generating word line (WL) control signals based on a row address from an external device, a first sub-array including memory cells connected to word lines, a first sub-word line driver (SWD) providing a selection voltage or a non-selection voltage to odd-numbered word lines of the word lines based on odd-numbered WL control signals corresponding to the odd-numbered word lines, and a second SWD providing the selection voltage or the non-selection voltage to even-numbered word lines of the word lines based on even-numbered WL control signals corresponding to the even-numbered word lines. The first SWD applies the non-selection voltage to non-selection word lines of the even-numbered word lines, in response to the even-numbered WL control signals, and the second SWD applies the non-selection voltage to non-selection word lines of the odd-numbered word lines, in response to the odd-numbered WL control signals.

公开(公告)号：US20230354582A1

公开(公告)日：2023-11-02

申请号：US18062825

申请日：2022-12-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiseok Lee ,  Byeongjoo Ku ,  Keunnam Kim ,  Wonsok Lee ,  Moonyoung Jeong ,  Min Hee Cho

IPC: H01L29/94

CPC classification number: H10B12/315 ,  H10B12/05

Abstract: A semiconductor device may include a bit line extending in a first direction, a semiconductor pattern on the bit line, the semiconductor pattern including first and second vertical portions, which are opposite to each other in the first direction, and a horizontal portion connecting the first and second vertical portions, first and second word lines on the horizontal portion to be adjacent to the first and second vertical portions, respectively, and a gate insulating pattern between the first vertical portion and the first word line and between the second vertical portion and the second word line. A bottom surface of the horizontal portion may be located at a height that is lower than or equal to the uppermost surface of the bit line.

公开(公告)号：US11696434B2

公开(公告)日：2023-07-04

申请号：US17241860

申请日：2021-04-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiseok Lee ,  Kyunghwan Lee ,  Dongoh Kim ,  Yongseok Kim ,  Hui-Jung Kim ,  Min Hee Cho

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/395 ,  H10B12/50

Abstract: A semiconductor memory device includes a bit line extending in a first direction, a channel pattern on the bit line, the channel pattern including first and second vertical portions facing each other and a horizontal portion connecting the first and second vertical portions, first and second word lines provided on the horizontal portion and between the first and second vertical portions and extended in a second direction crossing the bit line, and a gate insulating pattern provided between the first word line and the channel pattern and between the second word line and the channel pattern.