公开(公告)号：US12199127B2

公开(公告)日：2025-01-14

申请号：US17528237

申请日：2021-11-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeongsoon Kang ,  Mintae Ryu ,  Minsu Lee ,  Wonsok Lee

IPC: H01L27/146 ,  H01L27/148

Abstract: An image sensor includes a first substrate. A photoelectric conversion region is in the first substrate. A first interlayer insulating layer is on the first substrate. A transistor includes a bonding insulating layer on the first interlayer insulating layer, a semiconductor layer on the bonding insulating layer, and a first gate on the semiconductor layer. A bias pad is spaced apart from the semiconductor layer by the bonding insulating layer. The bias pad overlaps the first gate in a planar view. A second interlayer insulating layer covers the transistor.

公开(公告)号：US12166132B2

公开(公告)日：2024-12-10

申请号：US17690371

申请日：2022-03-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhee Cho ,  Mintae Ryu ,  Sungwon Yoo ,  Wonsok Lee ,  Hyunmog Park ,  Kiseok Lee

IPC: H01L29/786

Abstract: A semiconductor device including a conductive line on a substrate, a first gate electrode on the conductive line, a second gate electrode separated by a gate isolation insulating layer on the first gate electrode, a first channel layer on a side surface of the first gate electrode, with a first gate insulating layer therebetween, a first source/drain region on another side surface of the first gate electrode, a second channel layer on another side surface of the second gate electrode on a side that is opposite to the first channel layer, with a second gate insulating layer therebetween, a second source/drain region on the second channel layer, and a third source/drain region on the first channel layer and on a side surface of the second gate electrode on a same side as the first channel layer may be provided.

公开(公告)号：US20240397708A1

公开(公告)日：2024-11-28

申请号：US18402790

申请日：2024-01-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juho Lee ,  Seongjae Byeon ,  Wonsok Lee ,  Jeon IL Lee

IPC: H10B12/00

Abstract: A semiconductor memory device includes a bit line on a substrate and extending in a first direction parallel to a top surface of the substrate, a channel pattern connected to a top surface of the bit line and extending in a second direction perpendicular to the top surface of the substrate, a first drain pattern on the channel pattern, a first word line adjacent to a lower portion of the first drain pattern and the channel pattern, and a gate insulating layer between the lower portion of the first drain pattern and the first word line and between the channel pattern and the first word line. An energy band gap of a first material of the first drain pattern is greater than an energy band gap of a second material of the channel pattern.

公开(公告)号：US20220384661A1

公开(公告)日：2022-12-01

申请号：US17578893

申请日：2022-01-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhee Cho ,  Kiseok Lee ,  Wonsok Lee ,  Mintae Ryu ,  Hyunmog Park ,  Woobin Song ,  Sungwon Yoo

IPC: H01L29/786 ,  H01L27/108 ,  H01L29/423 ,  H01L29/66

Abstract: A semiconductor device includes: a conductive line that extends in a first direction on a substrate; an insulating pattern layer on the substrate and having a trench that extends in a second direction, the trench having an extension portion that extends into the conductive line; a channel layer on opposite sidewalls of the trench and connected to a region, exposed by the trench, of the conductive line; first and second gate electrodes on the channel layer, and respectively along the opposite sidewalls of the trench; a gate insulating layer between the channel layer and the first and second gate electrodes; a buried insulating layer between the first and second gate electrodes within the trench; and a first contact and a second contact, respectively buried in the insulating pattern layer, and respectively connected to upper regions of the channel layer.

公开(公告)号：US10068038B2

公开(公告)日：2018-09-04

申请号：US15277480

申请日：2016-09-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Hwan Jang ,  Sungchul Kim ,  Jiseong Doh ,  Wonsok Lee

IPC: G06F17/50

Abstract: A semiconductor process simulation method includes classifying a semiconductor process simulation into a plurality of blocks based on an annealing simulation, performing a shape simulation corresponding to a block selected from the plurality of blocks, and performing at least two ion implantation simulations among a plurality of ion implantation simulations corresponding to the selected block in parallel, based on result data of the shape simulation corresponding to the selected block.

公开(公告)号：US20160086841A1

公开(公告)日：2016-03-24

申请号：US14711394

申请日：2015-05-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SEUNGHYUN SONG ,  Hyeon Kyun Noh ,  Taeyong Kwon ,  Sangsu Kim ,  Shigenobu Maeda ,  Krishna Bhuwalka ,  Uihui Kwon ,  Keunho Lee ,  Wonsok Lee

IPC: H01L21/762 ,  H01L29/10 ,  H01L21/02 ,  H01L29/06 ,  H01L21/308 ,  H01L29/66

CPC classification number: H01L21/76224 ,  H01L21/3086 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method for forming a pattern of a semiconductor device and a semiconductor device formed using the same are provided. The method includes forming a buffer layer on a substrate, forming a channel layer on the buffer layer, forming support patterns penetrating the channel layer, and forming channel fin patterns and a buffer pattern by patterning the channel layer and the buffer layer. The channel layer includes a material of which a lattice constant is different from that of the buffer layer, and each of the channel fin patterns has both sidewalls that are in contact with the support patterns and are opposite to each other.

Abstract translation: 提供了一种用于形成半导体器件的图案的方法和使用其形成的半导体器件。 该方法包括在衬底上形成缓冲层，在缓冲层上形成沟道层，形成穿透沟道层的支撑图案，并通过图案化沟道层和缓冲层形成沟道鳍图案和缓冲图案。 沟道层包括晶格常数与缓冲层的晶格常数不同的材料，并且每个沟道鳍图案具有与支撑图案接触并且彼此相对的两个侧壁。

公开(公告)号：US20240395931A1

公开(公告)日：2024-11-28

申请号：US18425196

申请日：2024-01-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seongjae BYEON ,  Younggeun Song ,  Wonsok Lee ,  Juho Lee

IPC: H01L29/78 ,  H01L29/10 ,  H10B12/00

Abstract: A semiconductor device includes a substrate; a channel pattern on the substrate, the channel pattern having sidewalls extending in a vertical direction perpendicular to a surface of the substrate and a lower portion connecting lower portions of two sidewalls facing each other in a horizontal direction; a gate insulation layer pattern and a first conductive layer pattern sequentially stacked laterally on an inner sidewall of the channel pattern; and a second conductive layer pattern contacting at least an uppermost surface and an upper outer sidewall of the channel pattern, the second conductive pattern being spaced apart from the first conductive layer pattern.

公开(公告)号：US11785761B2

公开(公告)日：2023-10-10

申请号：US17240486

申请日：2021-04-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hui-Jung Kim ,  Min Hee Cho ,  Bong-Soo Kim ,  Junsoo Kim ,  Satoru Yamada ,  Wonsok Lee ,  Yoosang Hwang

IPC: H10B12/00 ,  H01L21/28 ,  H01L29/49 ,  H01L29/06

CPC classification number: H10B12/34 ,  H01L21/28088 ,  H01L29/0649 ,  H01L29/4966 ,  H10B12/053 ,  H10B12/315 ,  H10B12/488

Abstract: Semiconductor memory devices are provided. A semiconductor memory device includes an isolation layer in a first trench and a first gate electrode portion on the isolation layer. The semiconductor memory device includes a second gate electrode portion in a second trench. In some embodiments, the second gate electrode portion is wider, in a direction, than the first gate electrode portion. Moreover, in some embodiments, an upper region of the second trench is spaced apart from the first trench by a greater distance, in the direction, than a lower region of the second trench. Related methods of forming semiconductor memory devices are also provided.

公开(公告)号：US20220319575A1

公开(公告)日：2022-10-06

申请号：US17705915

申请日：2022-03-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minsu Lee ,  Min Tae Ryu ,  Wonsok Lee ,  Min Hee Cho

IPC: G11C11/408

Abstract: Disclosed is a memory device including a row decoder generating word line (WL) control signals based on a row address from an external device, a first sub-array including memory cells connected to word lines, a first sub-word line driver (SWD) providing a selection voltage or a non-selection voltage to odd-numbered word lines of the word lines based on odd-numbered WL control signals corresponding to the odd-numbered word lines, and a second SWD providing the selection voltage or the non-selection voltage to even-numbered word lines of the word lines based on even-numbered WL control signals corresponding to the even-numbered word lines. The first SWD applies the non-selection voltage to non-selection word lines of the even-numbered word lines, in response to the even-numbered WL control signals, and the second SWD applies the non-selection voltage to non-selection word lines of the odd-numbered word lines, in response to the odd-numbered WL control signals.

公开(公告)号：US11342330B2

公开(公告)日：2022-05-24

申请号：US17172124

申请日：2021-02-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min Hee Cho ,  Hyunmog Park ,  Woo Bin Song ,  Minsu Lee ,  Wonsok Lee

IPC: H01L27/108

Abstract: A semiconductor memory device is provided. The device may include a lower gate line provided on a substrate and extended in a first direction, an upper gate line vertically overlapped with the lower gate line and extended in the first direction, a first capacitor provided between the lower gate line and the upper gate line, a second capacitor provided between the lower gate line and the upper gate line and spaced apart from the first capacitor in the first direction, a lower semiconductor pattern provided to penetrate the lower gate line and connected to the first capacitor, an upper semiconductor pattern provided to penetrate the upper gate line and connected to the second capacitor, and a lower insulating pattern provided between the second capacitor and the lower gate line to cover the entire region of a bottom surface of the second capacitor.