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公开(公告)号：US10574270B1
公开(公告)日：2020-02-25
申请号：US15347743
申请日：2016-11-09
Applicant: Seagate Technology LLC
Inventor： Deepak Sridhara , Ara Patapoutian , Prafulla B Reddy , Richard Jay Parshall
IPC: H03M13/29 , G06F3/06 , G06F12/109
Abstract: Systems and methods are disclosed for implementing sector management in drives having multiple modulation coding. A circuit may be configured to generate a data sector having a first number of bits based on a first modulation encoding scheme associated with a first location of a data storage medium, determine a difference between the first number of bits and a second number of bits corresponding to a second modulation encoding scheme associated with a second location of the data storage medium, append a number of padding bits to the data sector based on the difference, and store the data sector to the second location of the data storage medium. The data sector may be a sector reallocated from the first location to the second location. The data sector may also be an intermediate parity sector stored to a media cache region of the data storage device.
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公开(公告)号：US10177791B1
公开(公告)日：2019-01-08
申请号：US15346651
申请日：2016-11-08
Applicant: Seagate Technology LLC
Inventor： Deepak Sridhara , Ara Patapoutian
Abstract: An apparatus may include a circuit that performs one or more read and recovery operations for one or more data segments including updating an outer code syndrome for one or more recovered data segments recovered by the one or more read and recovery operations and preventing updates of the outer code syndrome for one or more failed data segments not recovered by the one or more read and recovery operations.
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公开(公告)号：US11762731B2
公开(公告)日：2023-09-19
申请号：US17525443
申请日：2021-11-12
Applicant: Seagate Technology LLC
Inventor： Jason Bellorado , Deepak Sridhara
CPC classification number: G06F11/1004 , H03M13/2909
Abstract: Systems and methods are disclosed for an improved utilization of parity within a data storage device, and manufacturing methods thereof. In some embodiments, a data storage device can implement an improved codeword redundancy process that can be utilized for data storage locations which were not previously scanned for defects. In some embodiments, a data storage device can implement an improved codeword redundancy process to store write data to a data storage location without having to perform a read operation prior to storing the write data to the storage location. The improved codeword redundancy process can include various methods of storing or updating an outer code codeword for the data to be stored.
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公开(公告)号：US20230153196A1
公开(公告)日：2023-05-18
申请号：US17525443
申请日：2021-11-12
Applicant: Seagate Technology LLC
Inventor： Jason Bellorado , Deepak Sridhara
CPC classification number: G06F11/1004 , H03M13/2909
Abstract: Systems and methods are disclosed for an improved utilization of parity within a data storage device, and manufacturing methods thereof. In some embodiments, a data storage device can implement an improved codeword redundancy process that can be utilized for data storage locations which were not previously scanned for defects. In some embodiments, a data storage device can implement an improved codeword redundancy process to store write data to a data storage location without having to perform a read operation prior to storing the write data to the storage location. The improved codeword redundancy process can include various methods of storing or updating an outer code codeword for the data to be stored.
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公开(公告)号：US10951234B2
公开(公告)日：2021-03-16
申请号：US16245080
申请日：2019-01-10
Applicant: Seagate Technology LLC
Inventor： Deepak Sridhara , Rishi Ahuja , William M. Radich , Ara Patapoutian
Abstract: In one implementation, the disclosure provides a system including a detector configured to generate an output of a first log-likelihood ratio for each bit in an input data stream. The system also includes at least one look-up table providing a mapping of the first log-likelihood ratio to a second log-likelihood ratio. The mapping between the first log-likelihood ratio and the second log-likelihood ratio is non-linear. The system also includes a decoder configured to generate an output data stream using the second log-likelihood ratio to generate a value for each bit in the input data stream.
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Patent Agency Ranking
公开(公告)号：US10437674B1
公开(公告)日：2019-10-08
申请号：US15611733
申请日：2017-06-01
Applicant: Seagate Technology LLC
Inventor： Deepak Sridhara , Ara Patapoutian
Abstract: Systems and methods are disclosed for employing variable amounts of parity sectors. In certain embodiments, an apparatus may comprise a processor configured to generate a first number of parity sectors for write data to be written to a nonvolatile memory, and store the write data and a second number of parity sectors to the nonvolatile memory, the second number of parity sectors being a subset less than all of the first number of parity sectors. The processor may further select additional parity sectors from the first number of parity sectors based on error metrics for the write data, store the additional parity sectors to the nonvolatile memory, and perform error recovery on the write data based on the additional parity sectors.
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公开(公告)号：US09654145B1
公开(公告)日：2017-05-16
申请号：US14552207
申请日：2014-11-24
Applicant: Seagate Technology LLC
Inventor： Belkacem Derras , Deepak Sridhara , Richard Parshall
CPC classification number: G06F11/1048 , H03M13/2789
Abstract: A storage device disclosed herein includes a memory and a write channel configured to interleave a plurality of code-words to generate a plurality of multiplet sequences such that at least two of the plurality of code-words interleave to the end of the interleaving process. In one example implementation, for each of the multiplet sequences no two successive multiplets are from the same code-word, a multiplet including a plurality of bits from a single code-word.
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公开(公告)号：US20150089317A1
公开(公告)日：2015-03-26
申请号：US14032677
申请日：2013-09-20
Applicant: Seagate Technology LLC
Inventor： Ara Patapoutian , Deepak Sridhara , Zheng Wang , Jason Charles Jury
IPC: H03M13/23
CPC classification number: H03M13/353 , G11B20/1217 , G11B20/1833 , H03M13/1102 , H03M13/1515 , H03M13/152
Abstract: A storage device is configured to utilize different encoding and decoding schemes in reading and writing data to different regions of a storage device based on the position of the storage regions and/or component-specific physical characteristics of the regions. Each encoding scheme may include multiple different types of encoders selected based an optimization process for each region.
Abstract translation: 存储设备被配置为基于存储区域的位置和/或区域的组件特定物理特性来利用不同的编码和解码方案来将数据读取和写入存储设备的不同区域。 每个编码方案可以包括基于每个区域的优化处理选择的多种不同类型的编码器。
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公开(公告)号：US11314423B2
公开(公告)日：2022-04-26
申请号：US17000136
申请日：2020-08-21
Applicant: Seagate Technology LLC
Inventor： Jason Bellorado , Deepak Sridhara , Kinman Ng
Abstract: Sync-mark (SM) detection recovery techniques for HDDs tend to be slow and cumbersome. Typical approaches often require an entire read command to be aborted and multiple subsequent read commands with significant firmware intervention. Should a data sector be unreadable, an example recovery technique for HDDs is recursive read averaging (RRA). Using RRA, samples for failed sector reads are stored in memory. When a sector is subsequently read, the samples are averaged and replace the prior sample stored in memory. The averaged samples are then used to decode the sector. Should SMs associated with data fragments making up a sector be unreadable, the data fragments are unreadable, rendering the sector unreadable. The systems and methods described herein are used to recover previously unreadable SMs. When updated data fragments are subsequently recombined, the confidence level in the overall sector is improved, which increases the likelihood of a successful decode of the sector.
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公开(公告)号：US10944424B1
公开(公告)日：2021-03-09
申请号：US16142957
申请日：2018-09-26
Applicant: Seagate Technology LLC
Inventor： Zheng Wang , Ara Patapoutian , Deepak Sridhara
Abstract: Systems and methods are disclosed for error correction with multiple log likelihood ratio (LLR) lookup tables (LUTs) for a single read, which allows for adaptation to asymmetry in the number of 0 or 1 bit errors without re-read operations. In certain embodiments, an apparatus may comprise a circuit configured to receive a sequence of bit value estimates for data read from a solid state memory during a single read operation, generate a first sequence of LLR values by applying the sequence of bit value estimates to a first LUT, and perform a decoding operation on the first sequence of LLR values. When the first sequence of LLR values fails to decode, the circuit may be configured to generate a second sequence of LLR values by applying the bit value estimates to a second LUT, and perform the decoding operation on the second sequence of LLR values to generate decoded data.
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