公开(公告)号：US20240112646A1

公开(公告)日：2024-04-04

申请号：US18233359

申请日：2023-08-14

Applicant: Sharp Display Technology Corporation

Inventor： Jun NISHIMURA ,  Kengo HARA ,  Yohei TAKEUCHI ,  Yoshihito HARA ,  Tohru DAITOH

IPC: G09G3/36 ,  G06F3/041 ,  G09G3/20

CPC classification number: G09G3/3677 ,  G06F3/04166 ,  G09G3/2096 ,  G09G2310/0286 ,  G09G2330/021

Abstract: A set circuit in a unit circuit in a gate driver of a display device includes a setting transistor, a first auxiliary transistor, and a second auxiliary transistor. The setting transistor includes a source terminal connected to an internal node, a gate terminal connected to a set input terminal, and a drain terminal connected to the set input terminal via the first auxiliary transistor and also connected to an input terminal via the second auxiliary transistor in a diode-connected form. Each transistor is controlled to be in an on state and an off state during normal drive and is controlled to be in the off state and the on state during a pause period by a control signal supplied to the input terminal.

公开(公告)号：US20230252951A1

公开(公告)日：2023-08-10

申请号：US18101270

申请日：2023-01-25

Applicant: Sharp Display Technology Corporation

Inventor： Kengo HARA ,  Tohru DAITOH ,  Yoshihito HARA ,  Jun NISHIMURA ,  Yohei TAKEUCHI

IPC: G09G3/36 ,  H01L27/12

CPC classification number: G09G3/3677 ,  H01L27/124 ,  H01L27/1225 ,  G09G2310/0286 ,  G09G2330/021

Abstract: An active matrix substrate includes a gate driver including a shift register including a plurality of unit circuits connected in multiple stages. Each of the plurality of unit circuits includes an output node, a first node, a first TFT including a first gate terminal supplied with the set signal, a first source terminal connected to the first node, and a first drain terminal supplied with a first power supply potential higher than a low-level potential of the set signal, and a second TFT including a second gate terminal connected to the first node, a second source terminal connected to the output node, and a second drain terminal supplied with the clock signal. The first TFT includes a semiconductor layer, and a first and a second gate electrodes disposed on a side of the semiconductor layer opposite to the substrate and connected to the first gate terminal. The semiconductor layer includes a source contact region electrically connected to the first source terminal, a drain contact region electrically connected to the first drain terminal, and a first and a second channel regions separated from each other in a channel length direction between the contact regions when viewed from a normal direction of the substrate. The first gate electrode overlaps the first channel region via an upper gate insulating layer, and the second gate electrode overlaps the second channel region via the upper gate insulating layer.

公开(公告)号：US20230215395A1

公开(公告)日：2023-07-06

申请号：US18075300

申请日：2022-12-05

Applicant: Sharp Display Technology Corporation

Inventor： Jun NISHIMURA ,  Yoshihito HARA ,  Yohei TAKEUCHI ,  Kengo HARA ,  Tohru DAITOH

IPC: G09G3/36

CPC classification number: G09G3/3677 ,  G11C19/28

Abstract: A shift register includes stages each constituted by a unit circuit provided with thin-film transistors that separate a control node (i.e. a node that controls output from a unit circuit) into an output-side first control node and an input-side second control node. One of the thin-film transistors has a control terminal that is supplied with a set signal that is an output signal from a unit circuit constituting a preceding stage. The other of the thin-film transistors has a control terminal that is supplied with a reset signal that is an output signal from a unit circuit constituting a subsequent stage.

公开(公告)号：US20220342246A1

公开(公告)日：2022-10-27

申请号：US17717235

申请日：2022-04-11

Applicant: Sharp Display Technology Corporation

Inventor： Yoshihito HARA ,  Tohru DAITOH ,  Hajime IMAI ,  Teruyuki UEDA ,  Masaki MAEDA ,  Tatsuya KAWASAKI ,  Yoshiharu HIRATA

IPC: G02F1/1368 ,  G02F1/1343 ,  G02F1/1333 ,  G02F1/1362 ,  G02F1/1345 ,  G06F3/041 ,  G03F7/20

Abstract: An active matrix substrate includes a plurality of thin film transistors including an oxide semiconductor layer, an interlayer insulating layer, a plurality of pixel electrodes arranged above the interlayer insulating layer, a common electrode arranged between the pixel electrode and the interlayer insulating layer and also configured to function as a touch sensor electrode, a first dielectric layer arranged between the interlayer insulating layer and the common electrode, a second dielectric layer arranged between the common electrode and the pixel electrode, a plurality of touch wiring lines arranged between the interlayer insulating layer and the common electrode and formed of a third conductive film, and a plurality of pixel contact portions, in which each of the plurality of pixel contact portions includes a drain electrode of the thin film transistor, a connection electrode formed of the third conductive film and electrically connected to the drain electrode in a lower opening formed in the interlayer insulating layer, and a pixel electrode electrically connected to the connection electrode in an upper opening formed in the first dielectric layer and the second dielectric layer.