公开(公告)号：US20230317739A1

公开(公告)日：2023-10-05

申请号：US18130444

申请日：2023-04-04

Applicant: Sharp Display Technology Corporation

Inventor： Hajime IMAI ,  Tohru DAITOH ,  Yoshihito HARA ,  Tetsuo KIKUCHI ,  Teruyuki UEDA ,  Masaki MAEDA ,  Tatsuya KAWASAKI ,  Yoshiharu HIRATA

IPC: H01L27/12

CPC classification number: H01L27/1248 ,  H01L27/1288

Abstract: The active matrix substrate includes a plurality of oxide semiconductor TFTs supported by a substrate. Each of the plurality of oxide semiconductor TFTs includes an oxide semiconductor layer including a channel region, a lower electrode positioned between the oxide semiconductor layer and the substrate, and an insulating layer positioned between the oxide semiconductor layer and the lower electrode. The insulating layer has a layered structure including a lower layer, an upper layer positioned between the lower layer and the oxide semiconductor layer, and an intermediate layer positioned between the lower layer and the upper layer. The upper layer is a silicon oxide layer, the intermediate layer contains at least silicon and nitrogen, and the lower layer contains at least silicon, nitrogen, and oxygen. A hydrogen desorption amount in the lower layer is larger than a hydrogen desorption amount in the intermediate layer. Each of the hydrogen desorption amount of the lower layer and the hydrogen desorption amount of the intermediate layer is a desorption amount of hydrogen molecules per unit thickness in a range from 25° C. to 600° C. by TDS analysis.

公开(公告)号：US20220285405A1

公开(公告)日：2022-09-08

申请号：US17686485

申请日：2022-03-04

Applicant: Sharp Display Technology Corporation

Inventor： Hajime IMAI ,  Tohru DAITOH ,  Teruyuki UEDA ,  Yoshihito HARA ,  Masaki MAEDA ,  Tatsuya KAWASAKI ,  Yoshiharu HIRATA

IPC: H01L27/12 ,  G06F3/041

Abstract: An active matrix substrate includes a substrate and a plurality of oxide semiconductor TFTs supported on the substrate, in which each of oxide semiconductor TFT includes an oxide semiconductor layer including a first region and a second region having a specific resistance lower than a specific resistance of the first region, and a gate electrode disposed on at least a part of the first region with a gate insulating layer interposed therebetween, the gate insulating layer includes a first insulating layer and a second insulating layer disposed on the first insulating layer, and, when viewed from a normal direction of the substrate, the first insulating layer overlaps with the first region and does not overlap with the second region and the second insulating layer overlaps with the first region and at least a part of the second region.

公开(公告)号：US20230082232A1

公开(公告)日：2023-03-16

申请号：US17903085

申请日：2022-09-06

Applicant: Sharp Display Technology Corporation

Inventor： Tatsuya KAWASAKI ,  Tohru DAITOH ,  Hajime IMAI ,  Teruyuki UEDA ,  Masaki MAEDA ,  Yoshiharu HIRATA ,  Yoshihito HARA

IPC: G02F1/1362 ,  G02F1/1368 ,  H01L27/12

Abstract: An active matrix substrate includes pixel regions each including a pixel electrode and an oxide semiconductor TFT including an oxide semiconductor layer. Each pixel electrode is electrically connected to one of adjacent two of source bus lines. The oxide semiconductor layer in the oxide semiconductor TFT of each pixel region overlaps the pixel electrode of a first adjacent pixel region. The pixel electrode of the each pixel region partially overlaps the oxide semiconductor layer in a second adjacent pixel region. The source bus lines include first and second source bus lines adjacent to each other. Pixels sets each including two pixel regions whose pixel electrodes are connected to the first source bus line and pixel sets each including two pixel regions whose pixel electrodes are connected to the second source bus line are arranged alternately between the first and second source bus lines.

公开(公告)号：US20240337885A1

公开(公告)日：2024-10-10

申请号：US18746216

申请日：2024-06-18

Applicant: Sharp Display Technology Corporation

Inventor： Tatsuya KAWASAKI ,  Tohru DAITOH ,  Hajime IMAI ,  Teruyuki UEDA ,  Masaki MAEDA ,  Yoshiharu HIRATA ,  Yoshihito HARA

IPC: G02F1/1362 ,  G02F1/1343 ,  G02F1/1368 ,  G09G3/36 ,  H01L27/12

CPC classification number: G02F1/136286 ,  G02F1/134336 ,  G02F1/136213 ,  G02F1/13685 ,  G09G3/3614 ,  H01L27/1225

Abstract: An active matrix substrate includes pixel regions each including a pixel electrode and an oxide semiconductor TFT including an oxide semiconductor layer. Each pixel electrode is electrically connected to one of adjacent two of source bus lines. The oxide semiconductor layer in the oxide semiconductor TFT of each pixel region overlaps the pixel electrode of a first adjacent pixel region. The pixel electrode of the each pixel region partially overlaps the oxide semiconductor layer in a second adjacent pixel region. The source bus lines include first and second source bus lines adjacent to each other. Pixels sets each including two pixel regions whose pixel electrodes are connected to the first source bus line and pixel sets each including two pixel regions whose pixel electrodes are connected to the second source bus line are arranged alternately between the first and second source bus lines.

公开(公告)号：US20240331653A1

公开(公告)日：2024-10-03

申请号：US18585148

申请日：2024-02-23

Applicant: Sharp Display Technology Corporation

Inventor： Yohei TAKEUCHI ,  Tatsuya KAWASAKI ,  Kengo HARA ,  Masafumi SUGINO ,  Hajime IMAI ,  Tohru DAITOH

IPC: G09G3/36 ,  G02F1/1362 ,  G02F1/1368

CPC classification number: G09G3/3677 ,  G02F1/136286 ,  G02F1/1368 ,  G09G2310/0286 ,  G09G2310/08

Abstract: A transistor includes a first electrode, a first semiconductor portion that is at least partly superimposed on the first electrode and that is composed of a semiconductor material, a first insulating film that is interposed between the first electrode and the first semiconductor portion, a second electrode that is superimposed on a part of the first semiconductor portion and that is connected to the first semiconductor portion, and a third electrode that is located in a layer in which the second electrode is located, that is superimposed on a part of the first semiconductor portion, and that is connected to the first semiconductor portion. An electric potential of the second electrode is lower than that of the third electrode. The third electrode includes a first portion that is spaced from the second electrode and a second portion that is spaced from the second electrode opposite the first portion.

公开(公告)号：US20240152013A1

公开(公告)日：2024-05-09

申请号：US18416940

申请日：2024-01-19

Applicant: Sharp Display Technology Corporation

Inventor： Yoshihito HARA ,  Tohru DAITOH ,  Hajime IMAI ,  Teruyuki UEDA ,  Masaki MAEDA ,  Tatsuya KAWASAKI ,  Yoshiharu HIRATA

IPC: G02F1/1368 ,  G02F1/1333 ,  G02F1/1343 ,  G02F1/1345 ,  G02F1/1362 ,  G03F7/00 ,  G06F3/041

CPC classification number: G02F1/1368 ,  G02F1/133345 ,  G02F1/13338 ,  G02F1/134336 ,  G02F1/13454 ,  G02F1/136286 ,  G03F7/70 ,  G06F3/0412 ,  G02F2201/42 ,  G02F2202/10 ,  G06F3/04164 ,  G06F3/044

Abstract: An active matrix substrate includes a plurality of thin film transistors including an oxide semiconductor layer, an interlayer insulating layer, a plurality of pixel electrodes arranged above the interlayer insulating layer, a common electrode arranged between the pixel electrode and the interlayer insulating layer and also configured to function as a touch sensor electrode, a first dielectric layer arranged between the interlayer insulating layer and the common electrode, a second dielectric layer arranged between the common electrode and the pixel electrode, a plurality of touch wiring lines arranged between the interlayer insulating layer and the common electrode and formed of a third conductive film, and a plurality of pixel contact portions, in which each of the plurality of pixel contact portions includes a drain electrode of the thin film transistor, a connection electrode formed of the third conductive film and electrically connected to the drain electrode in a lower opening formed in the interlayer insulating layer, and a pixel electrode electrically connected to the connection electrode in an upper opening formed in the first dielectric layer and the second dielectric layer.

公开(公告)号：US20240414940A1

公开(公告)日：2024-12-12

申请号：US18696886

申请日：2021-12-06

Applicant: Sharp Display Technology Corporation

Inventor： Masaki MAEDA ,  Hajime IMAI ,  Yoshiharu HIRATA ,  Teruyuki UEDA ,  Tatsuya KAWASAKI ,  Tohru DAITOH

IPC: H10K59/121 ,  H01L27/12 ,  H10K59/131 ,  H10K59/80

Abstract: A display device includes: a base substrate; a thin-film transistor layer provided on the base substrate and having a first metal layer containing a copper film; and a light-emitting element layer provided on the thin-film transistor layer, and including a plurality of pixel electrodes, a plurality of light-emitting functional layers, and a common electrode, all of which are sequentially stacked on top of another and corresponding to a plurality of subpixels. A terminal unit includes a plurality of terminals formed of a same material as, and arranged in a same layer as, the first metal layer. Each of the pixel electrodes is formed of a second metal layer containing a silver film. On each of the terminals, a terminal protective layer formed of a transparent conductive film is provided.

公开(公告)号：US20220342246A1

公开(公告)日：2022-10-27

申请号：US17717235

申请日：2022-04-11

Applicant: Sharp Display Technology Corporation

Inventor： Yoshihito HARA ,  Tohru DAITOH ,  Hajime IMAI ,  Teruyuki UEDA ,  Masaki MAEDA ,  Tatsuya KAWASAKI ,  Yoshiharu HIRATA

IPC: G02F1/1368 ,  G02F1/1343 ,  G02F1/1333 ,  G02F1/1362 ,  G02F1/1345 ,  G06F3/041 ,  G03F7/20

Abstract: An active matrix substrate includes a plurality of thin film transistors including an oxide semiconductor layer, an interlayer insulating layer, a plurality of pixel electrodes arranged above the interlayer insulating layer, a common electrode arranged between the pixel electrode and the interlayer insulating layer and also configured to function as a touch sensor electrode, a first dielectric layer arranged between the interlayer insulating layer and the common electrode, a second dielectric layer arranged between the common electrode and the pixel electrode, a plurality of touch wiring lines arranged between the interlayer insulating layer and the common electrode and formed of a third conductive film, and a plurality of pixel contact portions, in which each of the plurality of pixel contact portions includes a drain electrode of the thin film transistor, a connection electrode formed of the third conductive film and electrically connected to the drain electrode in a lower opening formed in the interlayer insulating layer, and a pixel electrode electrically connected to the connection electrode in an upper opening formed in the first dielectric layer and the second dielectric layer.