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    ACTIVE MATRIX SUBSTRATE AND MANUFACTURING METHOD THEREOF
    2.
    发明公开
    ACTIVE MATRIX SUBSTRATE AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20230317739A1

    公开(公告)日：2023-10-05

    申请号：US18130444

    申请日：2023-04-04

    Applicant: Sharp Display Technology Corporation

    Inventor： Hajime IMAI ,  Tohru DAITOH ,  Yoshihito HARA ,  Tetsuo KIKUCHI ,  Teruyuki UEDA ,  Masaki MAEDA ,  Tatsuya KAWASAKI ,  Yoshiharu HIRATA

    IPC: H01L27/12

    CPC classification number: H01L27/1248 ,  H01L27/1288

    Abstract: The active matrix substrate includes a plurality of oxide semiconductor TFTs supported by a substrate. Each of the plurality of oxide semiconductor TFTs includes an oxide semiconductor layer including a channel region, a lower electrode positioned between the oxide semiconductor layer and the substrate, and an insulating layer positioned between the oxide semiconductor layer and the lower electrode. The insulating layer has a layered structure including a lower layer, an upper layer positioned between the lower layer and the oxide semiconductor layer, and an intermediate layer positioned between the lower layer and the upper layer. The upper layer is a silicon oxide layer, the intermediate layer contains at least silicon and nitrogen, and the lower layer contains at least silicon, nitrogen, and oxygen. A hydrogen desorption amount in the lower layer is larger than a hydrogen desorption amount in the intermediate layer. Each of the hydrogen desorption amount of the lower layer and the hydrogen desorption amount of the intermediate layer is a desorption amount of hydrogen molecules per unit thickness in a range from 25° C. to 600° C. by TDS analysis.

    SEMICONDUCTOR DEVICE
    3.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20220406942A1

    公开(公告)日：2022-12-22

    申请号：US17835273

    申请日：2022-06-08

    Applicant: Sharp Display Technology Corporation

    Inventor： Tetsuo KIKUCHI ,  Tohru DAITOH ,  Masahiko SUZUKI ,  Setsuji NISHIMIYA ,  Kengo HARA ,  Hitoshi TAKAHATA

    IPC: H01L29/786

    Abstract: Each first thin film transistor of a semiconductor device includes: a lower electrode; a first oxide semiconductor layer including a channel region and first and second contact regions; a gate electrode disposed on the channel region with a gate insulating layer interposed therebetween; and a source electrode and a drain electrode connected to the first contact region and the second contact region, respectively. When viewed from a normal direction of the substrate, at least a part of the channel region overlaps the lower electrode, and at least one of the first and second contact regions is located outside the lower electrode. The channel region has a layered structure including a lower layer, an upper layer located between the lower layer and the gate insulating layer, and a high mobility layer disposed between the lower layer and the upper layer and having mobility higher than mobility of the lower layer and the upper layer. In the channel region, the thickness of the upper layer is equal to or less than 1/3 of the thickness of the lower layer, and the thickness of the high mobility layer is equal to or less than 1/2 of the thickness of the lower layer.

    DISPLAY DEVICE
    4.
    发明申请
    DISPLAY DEVICE 有权

    公开(公告)号：US20240414940A1

    公开(公告)日：2024-12-12

    申请号：US18696886

    申请日：2021-12-06

    Applicant: Sharp Display Technology Corporation

    Inventor： Masaki MAEDA ,  Hajime IMAI ,  Yoshiharu HIRATA ,  Teruyuki UEDA ,  Tatsuya KAWASAKI ,  Tohru DAITOH

    IPC: H10K59/121 ,  H01L27/12 ,  H10K59/131 ,  H10K59/80

    Abstract: A display device includes: a base substrate; a thin-film transistor layer provided on the base substrate and having a first metal layer containing a copper film; and a light-emitting element layer provided on the thin-film transistor layer, and including a plurality of pixel electrodes, a plurality of light-emitting functional layers, and a common electrode, all of which are sequentially stacked on top of another and corresponding to a plurality of subpixels. A terminal unit includes a plurality of terminals formed of a same material as, and arranged in a same layer as, the first metal layer. Each of the pixel electrodes is formed of a second metal layer containing a silver film. On each of the terminals, a terminal protective layer formed of a transparent conductive film is provided.

    SEMICONDUCTOR DEVICE, DISPLAY DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
    5.
    发明公开
    SEMICONDUCTOR DEVICE, DISPLAY DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240154038A1

    公开(公告)日：2024-05-09

    申请号：US18378165

    申请日：2023-10-10

    Applicant: Sharp Display Technology Corporation

    Inventor： Tetsuo KIKUCHI ,  Tohru DAITOH ,  Masahiko SUZUKI ,  Setsuji NISHIMIYA ,  Hitoshi TAKAHATA

    IPC: H01L29/786 ,  G02F1/1368 ,  H01L29/417 ,  H01L29/66 ,  H10K59/121

    CPC classification number: H01L29/7869 ,  G02F1/1368 ,  H01L29/41733 ,  H01L29/6675 ,  H01L29/78696 ,  H10K59/1213

    Abstract: A semiconductor device includes a first TFT of a first conductivity type and a second TFT of a second conductivity type. The first TFT includes a first semiconductor layer made of an oxide semiconductor material of the first conductivity type, a first gate insulating layer provided on the first semiconductor layer, a first gate electrode located opposite to a channel region of the first semiconductor layer with the first gate insulating layer interposed therebetween, and a first source electrode. The second TFT includes a second semiconductor layer made of an oxide semiconductor material of the second conductivity type or a transparent semiconductor material of the second conductivity type, a second gate insulating layer provided on the second semiconductor layer, a second gate electrode located opposite to a channel region of the second semiconductor layer with the second gate insulating layer interposed therebetween, and a second source electrode. The first gate insulating layer includes a first layer and a second layer provided on the first layer. The second layer of the first gate insulating layer and the second gate insulating layer are provided in the same layer.

    ACTIVE MATRIX SUBSTRATE AND DISPLAY DEVICE
    7.
    发明公开
    ACTIVE MATRIX SUBSTRATE AND DISPLAY DEVICE 审中-公开

    公开(公告)号：US20230252951A1

    公开(公告)日：2023-08-10

    申请号：US18101270

    申请日：2023-01-25

    Applicant: Sharp Display Technology Corporation

    Inventor： Kengo HARA ,  Tohru DAITOH ,  Yoshihito HARA ,  Jun NISHIMURA ,  Yohei TAKEUCHI

    IPC: G09G3/36 ,  H01L27/12

    CPC classification number: G09G3/3677 ,  H01L27/124 ,  H01L27/1225 ,  G09G2310/0286 ,  G09G2330/021

    Abstract: An active matrix substrate includes a gate driver including a shift register including a plurality of unit circuits connected in multiple stages. Each of the plurality of unit circuits includes an output node, a first node, a first TFT including a first gate terminal supplied with the set signal, a first source terminal connected to the first node, and a first drain terminal supplied with a first power supply potential higher than a low-level potential of the set signal, and a second TFT including a second gate terminal connected to the first node, a second source terminal connected to the output node, and a second drain terminal supplied with the clock signal. The first TFT includes a semiconductor layer, and a first and a second gate electrodes disposed on a side of the semiconductor layer opposite to the substrate and connected to the first gate terminal. The semiconductor layer includes a source contact region electrically connected to the first source terminal, a drain contact region electrically connected to the first drain terminal, and a first and a second channel regions separated from each other in a channel length direction between the contact regions when viewed from a normal direction of the substrate. The first gate electrode overlaps the first channel region via an upper gate insulating layer, and the second gate electrode overlaps the second channel region via the upper gate insulating layer.

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