公开(公告)号：US20230352493A1

公开(公告)日：2023-11-02

申请号：US18140593

申请日：2023-04-27

Applicant: Sharp Display Technology Corporation

Inventor： Yoshihito HARA ,  Tohru DAITOH ,  Jun NISHIMURA ,  Kengo HARA ,  Yohei TAKEUCHI

IPC: H01L27/12 ,  G02F1/1368 ,  G02F1/1362 ,  G02F1/1337 ,  G02F1/1343 ,  G02F1/1333 ,  G02F1/1335 ,  G06F3/041 ,  G06F3/044

CPC classification number: H01L27/1248 ,  G02F1/1368 ,  G02F1/136227 ,  G02F1/1337 ,  G02F1/134372 ,  G02F1/13338 ,  G02F1/136286 ,  G02F1/133512 ,  G02F1/136204 ,  G06F3/0412 ,  G06F3/04164 ,  G06F3/0446

Abstract: An active matrix substrate includes a thin film transistor including an oxide semiconductor layer, an interlayer insulating layer covering the thin film transistor, a pixel electrode provided above the interlayer insulating layer and electrically connected to the thin film transistor, a common electrode provided between the pixel electrode and the interlayer insulating layer, a first dielectric layer provided between the common electrode and the pixel electrode, and an alignment film covering the pixel electrode. The first dielectric layer includes a plurality of openings each of which exposes a part of the common electrode and includes the alignment film positioned therein.

公开(公告)号：US20250149007A1

公开(公告)日：2025-05-08

申请号：US18913037

申请日：2024-10-11

Applicant: Sharp Display Technology Corporation

Inventor： Kengo HARA ,  Tohru DAITOH ,  Yoshihito HARA ,  Jun NISHIMURA ,  Yohei TAKEUCHI

IPC: G09G3/36 ,  G06F3/041

Abstract: A display device includes: a display panel including a HIGH power supply line and a LOW power supply line; and a scan signal line drive circuit including a unit circuit, wherein the unit circuit includes: a SET terminal; a RESET terminal; an output terminal; a first thin film transistor; a second thin film transistor including a second semiconductor layer, a second gate electrode, a second source electrode, and a second drain electrode, the second gate electrode being electrically connected to the SET terminal, one of the second source electrode and the second drain electrode being electrically connected to an internal node; and a third thin film transistor, the second gate electrode is an upper gate electrode, another one of the second source electrode and the second drain electrode is electrically connected to the HIGH power supply line, and the second thin film transistor further includes a lower gate electrode.

公开(公告)号：US20240331653A1

公开(公告)日：2024-10-03

申请号：US18585148

申请日：2024-02-23

Applicant: Sharp Display Technology Corporation

Inventor： Yohei TAKEUCHI ,  Tatsuya KAWASAKI ,  Kengo HARA ,  Masafumi SUGINO ,  Hajime IMAI ,  Tohru DAITOH

IPC: G09G3/36 ,  G02F1/1362 ,  G02F1/1368

CPC classification number: G09G3/3677 ,  G02F1/136286 ,  G02F1/1368 ,  G09G2310/0286 ,  G09G2310/08

Abstract: A transistor includes a first electrode, a first semiconductor portion that is at least partly superimposed on the first electrode and that is composed of a semiconductor material, a first insulating film that is interposed between the first electrode and the first semiconductor portion, a second electrode that is superimposed on a part of the first semiconductor portion and that is connected to the first semiconductor portion, and a third electrode that is located in a layer in which the second electrode is located, that is superimposed on a part of the first semiconductor portion, and that is connected to the first semiconductor portion. An electric potential of the second electrode is lower than that of the third electrode. The third electrode includes a first portion that is spaced from the second electrode and a second portion that is spaced from the second electrode opposite the first portion.

公开(公告)号：US20230206875A1

公开(公告)日：2023-06-29

申请号：US18075307

申请日：2022-12-05

Applicant: Sharp Display Technology Corporation

Inventor： Jun NISHIMURA ,  Yoshihito HARA ,  Yohei TAKEUCHI ,  Kengo HARA ,  Tohru DAITOH

IPC: G09G3/36 ,  G11C19/28

CPC classification number: G09G3/3677 ,  G11C19/28 ,  G09G2310/0286 ,  G09G2300/0852

Abstract: A shift register includes stages each constituted by a unit circuit provided with a thin-film transistor (separation transistor) that separates a control node into an output-side first control node and an input-side second control node and a capacitor whose first end is connected to the second control node. The thin-film transistor (separation transistor) has a control terminal that is supplied with a high-level DC power supply voltage. Typically, the channel width of a thin-film transistor (first output control transistor) that controls output from a unit circuit is ten or more times greater than the channel width of the thin-film transistor (separation transistor).

公开(公告)号：US20240288738A1

公开(公告)日：2024-08-29

申请号：US18407420

申请日：2024-01-08

Applicant: Sharp Display Technology Corporation

Inventor： Kengo HARA ,  Tohru DAITOH ,  Yoshihito HARA ,  Jun NISHIMURA ,  Yohei TAKEUCHI

IPC: G02F1/1362 ,  G02F1/1368 ,  H01L27/12

CPC classification number: G02F1/13629 ,  G02F1/1368 ,  H01L27/124

Abstract: An active matrix substrate includes a pixel TFT provided corresponding to each pixel region, a pixel electrode electrically connected to the pixel TFT, a plurality of gate wirings extending in a row direction, and a plurality of source wirings extending in a column direction. Each gate wiring has a multilayer structure including a lower gate wiring electrically connected to a lower gate electrode included in the pixel TFT and an upper gate wiring electrically connected to an upper gate electrode included in the pixel TFT. In a case where the number of the gate wirings is defined as m and the number of the source wirings is defined as n, each gate wiring has 3 or more and less than n contact portions, each contact portion is positioned in any of n intersection regions, and the number of the contact portions overlapping each source wiring is less than m.

公开(公告)号：US20240112646A1

公开(公告)日：2024-04-04

申请号：US18233359

申请日：2023-08-14

Applicant: Sharp Display Technology Corporation

Inventor： Jun NISHIMURA ,  Kengo HARA ,  Yohei TAKEUCHI ,  Yoshihito HARA ,  Tohru DAITOH

IPC: G09G3/36 ,  G06F3/041 ,  G09G3/20

CPC classification number: G09G3/3677 ,  G06F3/04166 ,  G09G3/2096 ,  G09G2310/0286 ,  G09G2330/021

Abstract: A set circuit in a unit circuit in a gate driver of a display device includes a setting transistor, a first auxiliary transistor, and a second auxiliary transistor. The setting transistor includes a source terminal connected to an internal node, a gate terminal connected to a set input terminal, and a drain terminal connected to the set input terminal via the first auxiliary transistor and also connected to an input terminal via the second auxiliary transistor in a diode-connected form. Each transistor is controlled to be in an on state and an off state during normal drive and is controlled to be in the off state and the on state during a pause period by a control signal supplied to the input terminal.

公开(公告)号：US20230252951A1

公开(公告)日：2023-08-10

申请号：US18101270

申请日：2023-01-25

Applicant: Sharp Display Technology Corporation

Inventor： Kengo HARA ,  Tohru DAITOH ,  Yoshihito HARA ,  Jun NISHIMURA ,  Yohei TAKEUCHI

IPC: G09G3/36 ,  H01L27/12

CPC classification number: G09G3/3677 ,  H01L27/124 ,  H01L27/1225 ,  G09G2310/0286 ,  G09G2330/021

Abstract: An active matrix substrate includes a gate driver including a shift register including a plurality of unit circuits connected in multiple stages. Each of the plurality of unit circuits includes an output node, a first node, a first TFT including a first gate terminal supplied with the set signal, a first source terminal connected to the first node, and a first drain terminal supplied with a first power supply potential higher than a low-level potential of the set signal, and a second TFT including a second gate terminal connected to the first node, a second source terminal connected to the output node, and a second drain terminal supplied with the clock signal. The first TFT includes a semiconductor layer, and a first and a second gate electrodes disposed on a side of the semiconductor layer opposite to the substrate and connected to the first gate terminal. The semiconductor layer includes a source contact region electrically connected to the first source terminal, a drain contact region electrically connected to the first drain terminal, and a first and a second channel regions separated from each other in a channel length direction between the contact regions when viewed from a normal direction of the substrate. The first gate electrode overlaps the first channel region via an upper gate insulating layer, and the second gate electrode overlaps the second channel region via the upper gate insulating layer.

公开(公告)号：US20230215395A1

公开(公告)日：2023-07-06

申请号：US18075300

申请日：2022-12-05

Applicant: Sharp Display Technology Corporation

Inventor： Jun NISHIMURA ,  Yoshihito HARA ,  Yohei TAKEUCHI ,  Kengo HARA ,  Tohru DAITOH

IPC: G09G3/36

CPC classification number: G09G3/3677 ,  G11C19/28

Abstract: A shift register includes stages each constituted by a unit circuit provided with thin-film transistors that separate a control node (i.e. a node that controls output from a unit circuit) into an output-side first control node and an input-side second control node. One of the thin-film transistors has a control terminal that is supplied with a set signal that is an output signal from a unit circuit constituting a preceding stage. The other of the thin-film transistors has a control terminal that is supplied with a reset signal that is an output signal from a unit circuit constituting a subsequent stage.

公开(公告)号：US20220406267A1

公开(公告)日：2022-12-22

申请号：US17750449

申请日：2022-05-23

Applicant: Sharp Display Technology Corporation

Inventor： Yohei TAKEUCHI ,  Akira TAGAWA ,  Yasuaki IWASE ,  Jun NISHIMURA

IPC: G09G3/36

Abstract: A light control panel including an image display region including a region corresponding to an image display region in a display panel and a region corresponding to a peripheral circuit region in the display panel is provided between the display panel and a backlight. A pattern image for controlling radiation of light emitted from the backlight to the display panel is displayed in the image display region in the light control panel according to an action state of the peripheral circuit in the display panel.

公开(公告)号：US20220373832A1

公开(公告)日：2022-11-24

申请号：US17743517

申请日：2022-05-13

Applicant: Sharp Display Technology Corporation

Inventor： Jun NISHIMURA ,  Akira TAGAWA ,  Yasuaki IWASE ,  Yohei TAKEUCHI

IPC: G02F1/1368 ,  G02F1/1362 ,  G02F1/1343

Abstract: An active matrix substrate includes a first pixel region defined by first and second source bus lines adjacent to each other and first and second gate bus lines adjacent to each other and further includes a first pixel electrode and a first oxide semiconductor TFT that are associated with the first pixel region. The first oxide semiconductor TFT includes an oxide semiconductor layer and a gate electrode electrically connected to the first gate bus line. The oxide semiconductor layer includes a channel region and a low-resistance region including first and second regions located on opposite sides of the channel region. When viewed in a direction normal to the substrate, the low-resistance region extends across the first source bus line to another pixel region and partially overlaps a pixel electrode disposed in the other pixel region with an insulating layer interposed therebetween.