公开(公告)号：US20160021743A1

公开(公告)日：2016-01-21

申请号：US14583317

申请日：2014-12-26

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yu-Cheng Pai ,  Chun-Hsien Lin ,  Shih-Chao Chiu ,  Wei-Chung Hsiao ,  Ming-Chen Sun ,  Tzu-Chieh Shen ,  Chia-Cheng Chen

IPC: H05K1/11 ,  H05K3/46 ,  H05K3/40 ,  H05K1/02 ,  H05K3/02

CPC classification number: H01L21/6835 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/17 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H05K3/20 ,  H05K3/4007 ,  H05K3/4682 ,  H05K2201/0367 ,  H05K2201/09563 ,  H05K2201/10674

Abstract: A coreless packaging substrate is provided, which includes: a dielectric layer having opposite first and second surfaces; a first circuit layer embedded in the dielectric layer and exposed from the first surface of the dielectric layer, wherein the first circuit layer has a plurality of first conductive pads; a plurality of protruding elements formed on the first conductive pads, respectively, wherein each of the protruding elements has contact surfaces to be encapsulated by an external conductive element; a second circuit layer formed on the second surface of the dielectric layer; and a plurality of conductive vias formed in the dielectric layer for electrically connecting the first circuit layer and the second circuit layer. The present invention strengthens the bonding between the first conductive pads and the conductive elements due to a large contact area between the protruding elements and the conductive elements.

Abstract translation: 提供了一种无芯封装基板，其包括：具有相对的第一和第二表面的电介质层; 所述第一电路层嵌入在所述电介质层中并且从所述电介质层的所述第一表面露出，其中所述第一电路层具有多个第一导电焊盘; 分别形成在第一导电焊盘上的多个突起元件，其中每个突出元件具有被外部导电元件封装的接触表面; 形成在电介质层的第二表面上的第二电路层; 以及形成在电介质层中的多个导电通孔，用于电连接第一电路层和第二电路层。 本发明由于突出元件和导电元件之间的大的接触面积而增强了第一导电焊盘和导电元件之间的接合。

公开(公告)号：US20160013123A1

公开(公告)日：2016-01-14

申请号：US14562972

申请日：2014-12-08

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Yu-Cheng Pai ,  Chun-Hsien Lin ,  Shih-Chao Chiu ,  Wei-Chung Hsiao ,  Ming-Chen Sun ,  Tzu-Chieh Shen ,  Chia-Cheng Chen

IPC: H01L23/498 ,  H05K1/11 ,  H01L25/065 ,  H01L21/48 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/105 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/13 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5383 ,  H01L23/5389 ,  H01L24/16 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/1533 ,  H05K1/111 ,  H05K3/4697 ,  H05K2201/10674

Abstract: A method for fabricating a package structure is provided, which includes the steps of: providing a carrier having a plurality of bonding pads; laminating a dielectric layer on the carrier; forming a plurality of conductive posts in the dielectric layer; and forming a cavity in the dielectric layer to expose the bonding pads, wherein the conductive posts are positioned around a periphery of the cavity, thereby simplifying the fabrication process.

Abstract translation: 提供了一种制造封装结构的方法，其包括以下步骤：提供具有多个焊盘的载体; 在载体上层叠电介质层; 在所述电介质层中形成多个导电柱; 以及在所述电介质层中形成空腔以暴露所述接合焊盘，其中所述导电柱围绕所述空腔的周边定位，由此简化所述制造工艺。

公开(公告)号：US20150155250A1

公开(公告)日：2015-06-04

申请号：US14143700

申请日：2013-12-30

Applicant: Siliconware Precision Industries Co., Ltd

Inventor： Tzu-Chieh Chen ,  Shih-Chao Chiu ,  Chia-Cheng Chen

IPC: H01L23/00 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L24/32 ,  H01L21/4857 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/768 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5226 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/27 ,  H01L2221/68345 ,  H01L2224/04105 ,  H01L2224/16245 ,  H01L2224/73259 ,  H01L2224/81005 ,  H01L2224/92224 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/00

Abstract: A semiconductor package is provided, which includes: a first dielectric layer having opposite first and second surfaces and a cavity penetrating the first and second surfaces; a first circuit layer embedded in the first dielectric layer and exposed from the first surface of the first dielectric layer; at least an adhesive member formed in the cavity and adjacent to the first surface of the first dielectric layer; an electronic element disposed on the adhesive member; a second dielectric layer formed on the second surface of the first dielectric layer and in the cavity to encapsulate the adhesive member and the electronic element; a second circuit layer formed on the second dielectric layer; and a plurality of conductive vias formed in the second dielectric layer for electrically connecting the second circuit layer and the electronic element, thereby reducing the package size and cost and increasing the wiring space and flexibility.

Abstract translation: 提供一种半导体封装，其包括：具有相对的第一和第二表面的第一介电层和穿透第一表面和第二表面的空腔; 第一电路层，其被嵌入在所述第一电介质层中并从所述第一介电层的所述第一表面露出; 至少形成在所述空腔中并且与所述第一介电层的所述第一表面相邻的粘合构件; 设置在所述粘合构件上的电子元件; 第二电介质层，形成在所述第一介电层的所述第二表面上并且在所述空腔中，以封装所述粘合剂构件和所述电子元件; 形成在所述第二电介质层上的第二电路层; 以及形成在第二电介质层中的多个导电通孔，用于电连接第二电路层和电子元件，由此减小封装尺寸和成本并增加布线空间和柔性。

公开(公告)号：US11205644B2

公开(公告)日：2021-12-21

申请号：US16817001

申请日：2020-03-12

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chi-Rui Wu ,  Fu-Tang Huang ,  Chia-Cheng Chen ,  Chun-Hsien Lin ,  Hsuan-Hao Mi ,  Yu-Cheng Pai

IPC: H01L23/24 ,  H01L25/10 ,  H01L23/498 ,  H01L25/00 ,  H01L23/31 ,  H01L23/00

Abstract: An electronic package is provided, including: a first substrate having a first insulating portion; a first electronic component disposed on the first substrate; a second substrate having a second insulating portion and stacked on the first substrate through a plurality of conductive elements; and a first encapsulant formed between the first substrate and the second substrate. The first insulating portion of the first substrate differs in rigidity from the second insulating portion of the second substrate. As such, during a high temperature process, one of the first substrate and the second substrate pulls at the other to bend toward the same direction, thereby reducing warpage deviation of the overall electronic package. The present invention further provides a method for fabricating the electronic package.

公开(公告)号：US09899249B2

公开(公告)日：2018-02-20

申请号：US15334569

申请日：2016-10-26

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yu-Cheng Pai ,  Chun-Hsien Lin ,  Shih-Chao Chiu ,  Wei-Chung Hsiao ,  Ming-Chen Sun ,  Tzu-Chieh Shen ,  Chia-Cheng Chen

IPC: H01L21/683 ,  H05K3/40 ,  H01L23/498 ,  H01L21/48 ,  H05K3/46 ,  H05K3/20 ,  H01L23/00

CPC classification number: H01L21/6835 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/17 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H05K3/20 ,  H05K3/4007 ,  H05K3/4682 ,  H05K2201/0367 ,  H05K2201/09563 ,  H05K2201/10674

Abstract: A coreless packaging substrate is provided, which includes: a dielectric layer having opposite first and second surfaces; a first circuit layer embedded in the dielectric layer and exposed from the first surface of the dielectric layer, wherein the first circuit layer has a plurality of first conductive pads; a plurality of protruding elements formed on the first conductive pads, respectively, wherein each of the protruding elements has contact surfaces to be encapsulated by an external conductive element; a second circuit layer formed on the second surface of the dielectric layer; and a plurality of conductive vias formed in the dielectric layer for electrically connecting the first circuit layer and the second circuit layer. The present invention strengthens the bonding between the first conductive pads and the conductive elements due to a large contact area between the protruding elements and the conductive elements.

公开(公告)号：US20170287840A1

公开(公告)日：2017-10-05

申请号：US15621337

申请日：2017-06-13

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yu-Cheng Pai ,  Wei-Chung Hsiao ,  Shih-Chao Chiu ,  Chun-Hsien Lin ,  Ming-Chen Sun ,  Tzu-Chieh Shen ,  Chia-Cheng Chen

IPC: H01L23/538 ,  H01L23/00

CPC classification number: H01L23/5389 ,  H01L21/568 ,  H01L23/3128 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/16227 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2224/81

Abstract: A semiconductor package structure and a method of fabricating the same are provided. The semiconductor package structure includes a package body having opposing first and second surfaces; a plurality of first conductive pads and a plurality of second conductive pads formed on the first surface of the package body; a semiconductor component embedded in the package body and electrically connected to the first conductive pads; and a plurality of conductive elements embedded in the package body, each of the conductive elements having a first end electrically connected to a corresponding one of the second conductive pads and a second end opposing the first end and exposed from the second surface of the package body. Since the semiconductor component is embedded in the package body, the thickness of the semiconductor package structure is reduced.

公开(公告)号：US20170171981A1

公开(公告)日：2017-06-15

申请号：US15393429

申请日：2016-12-29

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chun-Hsien Lin ,  Shih-Chao Chiu ,  Yu-Cheng Pai ,  Tzu-Chieh Shen ,  Chia-Cheng Chen

IPC: H05K3/00 ,  H05K3/28 ,  H05K3/46 ,  H05K3/18 ,  H05K3/40

CPC classification number: H05K3/007 ,  H05K1/0271 ,  H05K3/0026 ,  H05K3/188 ,  H05K3/28 ,  H05K3/4038 ,  H05K3/4682 ,  H05K2203/0152 ,  H05K2203/016 ,  H05K2203/1377

Abstract: The present invention provides a substrate structure and a method of fabricating the substrate structure. The method includes: forming a first wiring layer on a first carrier, forming a dielectric layer on the first wiring layer, forming a second wiring layer on the dielectric layer, forming an insulating protection layer on the second wiring layer, forming a second carrier on the insulating protection layer, and removing the first carrier. The formation of the second carrier provides the substrate structure with adequate rigidity to avoid breakage or warpage such that the miniaturization requirement can be satisfied.

公开(公告)号：US09673140B2

公开(公告)日：2017-06-06

申请号：US14620328

申请日：2015-02-12

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chia-Cheng Chen ,  Ming-Chen Sun ,  Tzu-Chieh Shen ,  Shih-Chao Chiu ,  Wei-Chung Hsiao ,  Yu-Cheng Pai ,  Don-Son Jiang

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/538 ,  H01L23/00 ,  H01L25/10 ,  H01L25/16

CPC classification number: H01L23/49811 ,  H01L21/4853 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L24/92 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1076 ,  H01L2924/15156 ,  H01L2924/15159 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/19103 ,  H01L2924/37001 ,  H01L2924/014

Abstract: A method for fabricating a package structure is provided, which includes the steps of: providing a carrier having a plurality of bonding pads; laminating a laminate on the carrier, wherein the laminate has a built-up portion and a release portion smaller in size than the built-up portion, the release portion covering the bonding pads and the built-up portion being laminated on the release portion and the carrier; forming a plurality of conductive posts in the built-up portion; and removing the release portion and the built-up portion on the release portion such that a cavity is formed in the laminate to expose the bonding pads, the conductive posts being positioned around a periphery of the cavity. Therefore, the present invention has simplified processes.

公开(公告)号：US09510463B2

公开(公告)日：2016-11-29

申请号：US14583317

申请日：2014-12-26

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yu-Cheng Pai ,  Chun-Hsien Lin ,  Shih-Chao Chiu ,  Wei-Chung Hsiao ,  Ming-Chen Sun ,  Tzu-Chieh Shen ,  Chia-Cheng Chen

IPC: H01L23/498 ,  H05K3/40 ,  H05K3/46 ,  H05K3/20

CPC classification number: H01L21/6835 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/17 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H05K3/20 ,  H05K3/4007 ,  H05K3/4682 ,  H05K2201/0367 ,  H05K2201/09563 ,  H05K2201/10674

Abstract: A coreless packaging substrate is provided, which includes: a dielectric layer having opposite first and second surfaces; a first circuit layer embedded in the dielectric layer and exposed from the first surface of the dielectric layer, wherein the first circuit layer has a plurality of first conductive pads; a plurality of protruding elements formed on the first conductive pads, respectively, wherein each of the protruding elements has contact surfaces to be encapsulated by an external conductive element; a second circuit layer formed on the second surface of the dielectric layer; and a plurality of conductive vias formed in the dielectric layer for electrically connecting the first circuit layer and the second circuit layer. The present invention strengthens the bonding between the first conductive pads and the conductive elements due to a large contact area between the protruding elements and the conductive elements.

Abstract translation: 提供了一种无芯封装基板，其包括：具有相对的第一和第二表面的电介质层; 所述第一电路层嵌入在所述电介质层中并且从所述电介质层的所述第一表面露出，其中所述第一电路层具有多个第一导电焊盘; 分别形成在第一导电焊盘上的多个突起元件，其中每个突出元件具有被外部导电元件封装的接触表面; 形成在电介质层的第二表面上的第二电路层; 以及形成在电介质层中的多个导电通孔，用于电连接第一电路层和第二电路层。 本发明由于突出元件和导电元件之间的大的接触面积而增强了第一导电焊盘和导电元件之间的接合。

公开(公告)号：US20150287671A1

公开(公告)日：2015-10-08

申请号：US14620328

申请日：2015-02-12

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chia-Cheng Chen ,  Ming-Chen Sun ,  Tzu-Chieh Shen ,  Shih-Chao Chiu ,  Wei-Chung Hsiao ,  Yu-Cheng Pai ,  Don-Son Jiang

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/492

CPC classification number: H01L23/49811 ,  H01L21/4853 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L24/92 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1076 ,  H01L2924/15156 ,  H01L2924/15159 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/19103 ,  H01L2924/37001 ,  H01L2924/014

Abstract: A method for fabricating a package structure is provided, which includes the steps of: providing a carrier having a plurality of bonding pads; laminating a laminate on the carrier, wherein the laminate has a built-up portion and a release portion smaller in size than the built-up portion, the release portion covering the bonding pads and the built-up portion being laminated on the release portion and the carrier; forming a plurality of conductive posts in the built-up portion; and removing the release portion and the built-up portion on the release portion such that a cavity is formed in the laminate to expose the bonding pads, the conductive posts being positioned around a periphery of the cavity. Therefore, the present invention has simplified processes.

Abstract translation: 提供了一种制造封装结构的方法，其包括以下步骤：提供具有多个焊盘的载体; 在载体上层叠层压体，其中层压体具有积累部分和尺寸小于组合部分的剥离部分，覆盖接合焊盘的释放部分和积层部分层压在释放部分上， 承运人 在所述积层部中形成多个导电柱; 以及在所述释放部分上移除所述释放部分和所述积累部分，使得在所述层压体中形成空腔以露出所述接合焊盘，所述导电柱位于所述空腔的周边周围。 因此，本发明具有简化的处理。