公开(公告)号：US20170047240A1

公开(公告)日：2017-02-16

申请号：US15334569

申请日：2016-10-26

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yu-Cheng Pai ,  Chun-Hsien Lin ,  Shih-Chao Chiu ,  Wei-Chung Hsiao ,  Ming-Chen Sun ,  Tzu-Chieh Shen ,  Chia-Cheng Chen

IPC: H01L21/683 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L21/6835 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/17 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H05K3/20 ,  H05K3/4007 ,  H05K3/4682 ,  H05K2201/0367 ,  H05K2201/09563 ,  H05K2201/10674

Abstract: A coreless packaging substrate is provided, which includes: a dielectric layer having opposite first and second surfaces; a first circuit layer embedded in the dielectric layer and exposed from the first surface of the dielectric layer, wherein the first circuit layer has a plurality of first conductive pads; a plurality of protruding elements formed on the first conductive pads, respectively, wherein each of the protruding elements has contact surfaces to be encapsulated by an external conductive element; a second circuit layer formed on the second surface of the dielectric layer; and a plurality of conductive vias formed in the dielectric layer for electrically connecting the first circuit layer and the second circuit layer. The present invention strengthens the bonding between the first conductive pads and the conductive elements due to a large contact area between the protruding elements and the conductive elements.

Abstract translation: 提供了一种无芯封装基板，其包括：具有相对的第一和第二表面的电介质层; 所述第一电路层嵌入在所述电介质层中并且从所述电介质层的所述第一表面露出，其中所述第一电路层具有多个第一导电焊盘; 分别形成在第一导电焊盘上的多个突起元件，其中每个突出元件具有被外部导电元件封装的接触表面; 形成在电介质层的第二表面上的第二电路层; 以及形成在电介质层中的多个导电通孔，用于电连接第一电路层和第二电路层。 本发明由于突出元件和导电元件之间的大的接触面积而增强了第一导电焊盘和导电元件之间的接合。

公开(公告)号：US20160225642A1

公开(公告)日：2016-08-04

申请号：US14981043

申请日：2015-12-28

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yu-Cheng Pai

IPC: H01L21/48 ,  H01L23/495 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L21/4832 ,  H01L21/4825 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/49548 ,  H01L23/49568 ,  H01L23/49582 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2224/85464 ,  H01L2224/8549 ,  H01L2924/00014 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method for fabricating an electronic package structure is provided, which includes the steps of: forming a circuit layer on a conductor; disposing an electronic element on the circuit layer; forming an insulating layer on the conductor to encapsulate the electronic element and the circuit layer; and removing portions of the conductor so as to cause the remaining portions of the conductor to constitute a plurality of conductive bumps. As such, when the electronic package structure is disposed on a circuit board through an SMT (Surface Mount Technology) process, the conductive bumps are easily aligned with contacts of the circuit board, thereby effectively improving the yield of the SMT process.

Abstract translation: 提供了一种制造电子封装结构的方法，其包括以下步骤：在导体上形成电路层; 在电路层上设置电子元件; 在导体上形成绝缘层以封装电子元件和电路层; 并且去除导体的部分，以使导体的其余部分构成多个导电凸块。 这样，当通过SMT（表面贴装技术）工艺将电子封装结构设置在电路板上时，导电凸块容易与电路板的触点对准，从而有效地提高了SMT工艺的成品率。

公开(公告)号：US20160118323A1

公开(公告)日：2016-04-28

申请号：US14833103

申请日：2015-08-23

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yu-Cheng Pai

IPC: H01L23/498 ,  H01L23/31 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L21/4853 ,  H01L21/4846 ,  H01L21/486 ,  H01L21/56 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/3178 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49894 ,  H01L24/11 ,  H01L24/17 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/16237 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2924/15311 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A method for fabricating a package structure is provided, which includes the steps of: forming a first insulating layer on a carrier; forming a dielectric body on the first insulating layer, wherein the dielectric body has a first surface formed on the first insulating layer and a second surface opposite to the first surface, and a circuit layer and a plurality of conductive posts formed on the circuit layer are embedded in the dielectric body; forming a second insulating layer on the second surface of the dielectric body, wherein the glass transition temperature of the first insulating layer and/or the second insulating layer is greater than 250° C.; and removing the carrier. Since the glass transition temperature of the first or second insulating layer is greater than that of the dielectric body, the package structure has a preferred strength to avoid warping, thereby dispensing with a support member.

Abstract translation: 提供一种制造封装结构的方法，其包括以下步骤：在载体上形成第一绝缘层; 在所述第一绝缘层上形成绝缘体，其中所述电介质体具有形成在所述第一绝缘层上的第一表面和与所述第一表面相对的第二表面，以及形成在所述电路层上的电路层和多个导电柱 嵌入介电体内; 在所述绝缘体的第二表面上形成第二绝缘层，其中所述第一绝缘层和/或所述第二绝缘层的玻璃化转变温度大于250℃; 并移除载体。 由于第一绝缘层或第二绝缘层的玻璃化转变温度大于绝缘体的玻璃化转变温度，因此封装结构具有优选的强度以避免翘曲，从而分配支撑构件。

公开(公告)号：US20160021743A1

公开(公告)日：2016-01-21

申请号：US14583317

申请日：2014-12-26

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yu-Cheng Pai ,  Chun-Hsien Lin ,  Shih-Chao Chiu ,  Wei-Chung Hsiao ,  Ming-Chen Sun ,  Tzu-Chieh Shen ,  Chia-Cheng Chen

IPC: H05K1/11 ,  H05K3/46 ,  H05K3/40 ,  H05K1/02 ,  H05K3/02

CPC classification number: H01L21/6835 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/17 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H05K3/20 ,  H05K3/4007 ,  H05K3/4682 ,  H05K2201/0367 ,  H05K2201/09563 ,  H05K2201/10674

Abstract: A coreless packaging substrate is provided, which includes: a dielectric layer having opposite first and second surfaces; a first circuit layer embedded in the dielectric layer and exposed from the first surface of the dielectric layer, wherein the first circuit layer has a plurality of first conductive pads; a plurality of protruding elements formed on the first conductive pads, respectively, wherein each of the protruding elements has contact surfaces to be encapsulated by an external conductive element; a second circuit layer formed on the second surface of the dielectric layer; and a plurality of conductive vias formed in the dielectric layer for electrically connecting the first circuit layer and the second circuit layer. The present invention strengthens the bonding between the first conductive pads and the conductive elements due to a large contact area between the protruding elements and the conductive elements.

Abstract translation: 提供了一种无芯封装基板，其包括：具有相对的第一和第二表面的电介质层; 所述第一电路层嵌入在所述电介质层中并且从所述电介质层的所述第一表面露出，其中所述第一电路层具有多个第一导电焊盘; 分别形成在第一导电焊盘上的多个突起元件，其中每个突出元件具有被外部导电元件封装的接触表面; 形成在电介质层的第二表面上的第二电路层; 以及形成在电介质层中的多个导电通孔，用于电连接第一电路层和第二电路层。 本发明由于突出元件和导电元件之间的大的接触面积而增强了第一导电焊盘和导电元件之间的接合。

公开(公告)号：US20160013123A1

公开(公告)日：2016-01-14

申请号：US14562972

申请日：2014-12-08

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Yu-Cheng Pai ,  Chun-Hsien Lin ,  Shih-Chao Chiu ,  Wei-Chung Hsiao ,  Ming-Chen Sun ,  Tzu-Chieh Shen ,  Chia-Cheng Chen

IPC: H01L23/498 ,  H05K1/11 ,  H01L25/065 ,  H01L21/48 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/105 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/13 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5383 ,  H01L23/5389 ,  H01L24/16 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/1533 ,  H05K1/111 ,  H05K3/4697 ,  H05K2201/10674

Abstract: A method for fabricating a package structure is provided, which includes the steps of: providing a carrier having a plurality of bonding pads; laminating a dielectric layer on the carrier; forming a plurality of conductive posts in the dielectric layer; and forming a cavity in the dielectric layer to expose the bonding pads, wherein the conductive posts are positioned around a periphery of the cavity, thereby simplifying the fabrication process.

Abstract translation: 提供了一种制造封装结构的方法，其包括以下步骤：提供具有多个焊盘的载体; 在载体上层叠电介质层; 在所述电介质层中形成多个导电柱; 以及在所述电介质层中形成空腔以暴露所述接合焊盘，其中所述导电柱围绕所述空腔的周边定位，由此简化所述制造工艺。

公开(公告)号：US20230027120A1

公开(公告)日：2023-01-26

申请号：US17411322

申请日：2021-08-25

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Shao-Tzu Tang ,  Wen-Jung Tsai ,  Chih-Hsien Chiu ,  Ko-Wei Chang ,  Yu-Wei Yeh ,  Yu-Cheng Pai ,  Chuan-Yi Pan ,  Chi-Rui Wu

IPC: H01Q1/22 ,  H01L23/552

Abstract: An electronic package is provided, in which a carrier structure provided with electronic components is disposed onto an antenna structure, where a stepped portion is formed at an edge of the antenna structure, so that a shielding body is arranged along a surface of the stepped portion. Therefore, the shielding body only covers a part of the surface of the antenna structure to prevent the shielding body from interfering with operation of the antenna structure.

公开(公告)号：US20200212019A1

公开(公告)日：2020-07-02

申请号：US16817001

申请日：2020-03-12

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chi-Rui Wu ,  Fu-Tang Huang ,  Chia-Cheng Chen ,  Chun-Hsien Lin ,  Hsuan-Hao Mi ,  Yu-Cheng Pai

IPC: H01L25/10 ,  H01L23/24 ,  H01L23/498 ,  H01L25/00

Abstract: An electronic package is provided, including: a first substrate having a first insulating portion; a first electronic component disposed on the first substrate; a second substrate having a second insulating portion and stacked on the first substrate through a plurality of conductive elements; and a first encapsulant formed between the first substrate and the second substrate. The first insulating portion of the first substrate differs in rigidity from the second insulating portion of the second substrate. As such, during a high temperature process, one of the first substrate and the second substrate pulls at the other to bend toward the same direction, thereby reducing warpage deviation of the overall electronic package. The present invention further provides a method for fabricating the electronic package.

公开(公告)号：US20200035573A1

公开(公告)日：2020-01-30

申请号：US16232735

申请日：2018-12-26

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Hsien-Lung Hsiao ,  Yu-Cheng Pai ,  Chia-Chi Lo ,  Szu-Hsien Chen ,  Shu-Chi Chang

IPC: H01L23/13 ,  H01L23/498 ,  H01L23/00

Abstract: A carrier structure includes: a plurality of substrates; a separation portion provided between the substrates; and a periphery portion provided at the periphery of the substrates and formed with at least one opening. With the configuration of the opening, the area of an insulating layer of the carrier structure can be reduced. Therefore, the overall space of electrostatic buildup in the carrier structure can also be reduced.

公开(公告)号：US20190164941A1

公开(公告)日：2019-05-30

申请号：US15938271

申请日：2018-03-28

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chi-Rui Wu ,  Fu-Tang Huang ,  Chia-Cheng Chen ,  Chun-Hsien Lin ,  Hsuan-Hao Mi ,  Yu-Cheng Pai

IPC: H01L25/10 ,  H01L23/498 ,  H01L25/00 ,  H01L23/24

Abstract: An electronic package is provided, including: a first substrate having a first insulating portion; a first electronic component disposed on the first substrate; a second substrate having a second insulating portion and stacked on the first substrate through a plurality of conductive elements; and a first encapsulant formed between the first substrate and the second substrate. The first insulating portion of the first substrate differs in rigidity from the second insulating portion of the second substrate. As such, during a high temperature process, one of the first substrate and the second substrate pulls at the other to bend toward the same direction, thereby reducing warpage deviation of the overall electronic package. The present invention further provides a method for fabricating the electronic package.

公开(公告)号：US10147615B2

公开(公告)日：2018-12-04

申请号：US15440390

申请日：2017-02-23

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yu-Cheng Pai

IPC: H01L21/48 ,  H01L23/498 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/00

Abstract: A method for fabricating a package structure is provided, which includes the steps of: forming a first insulating layer on a carrier; forming a dielectric body on the first insulating layer, wherein the dielectric body has a first surface formed on the first insulating layer and a second surface opposite to the first surface, and a circuit layer and a plurality of conductive posts formed on the circuit layer are embedded in the dielectric body; forming a second insulating layer on the second surface of the dielectric body, wherein the glass transition temperature of the first insulating layer and/or the second insulating layer is greater than 250° C.; and removing the carrier. Since the glass transition temperature of the first or second insulating layer is greater than that of the dielectric body, the package structure has a preferred strength to avoid warping, thereby dispensing with a support member.