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    Method of manufacturing flash memory device with reduced void generation
    12.
    发明授权
    Method of manufacturing flash memory device with reduced void generation 有权
    具有减少空穴产生的闪存器件的制造方法

    公开(公告)号：US07892959B2

    公开(公告)日：2011-02-22

    申请号：US12146183

    申请日：2008-06-25

    Applicant: Sung-Jin Kim

    Inventor： Sung-Jin Kim

    IPC: H01L21/3205 ,  H01L21/4763

    CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L27/115

    Abstract: A method of manufacturing a flash memory device that may include forming a first oxide film pattern and a first polysilicon pattern on a semiconductor substrate; sequentially forming a dielectric film pattern and a second polysilicon pattern on the semiconductor substrate including the first oxide film pattern and the first polysilicon pattern; forming a second oxide film pattern on the second polysilicon pattern; forming a gate by etching to the semiconductor substrate using the second oxide film pattern as a mask, the gate including the first oxide film pattern, the first polysilicon pattern, the dielectric film pattern and the second polysilicon pattern; removing the second oxide film pattern; forming a spacer on sidewalls of the gate; and forming an interlayer dielectric film on the semiconductor substrate including the gate and the spacer.

    Abstract translation: 一种制造闪存器件的方法，其可以包括在半导体衬底上形成第一氧化膜图案和第一多晶硅图案; 在包括第一氧化膜图案和第一多晶硅图案的半导体衬底上依次形成电介质膜图案和第二多晶硅图案; 在所述第二多晶硅图案上形成第二氧化膜图案; 通过使用第二氧化膜图案作为掩模通过蚀刻到半导体衬底来形成栅极，栅极包括第一氧化膜图案，第一多晶硅图案，电介质膜图案和第二多晶硅图案; 去除第二氧化膜图案; 在门的侧壁上形成间隔物; 以及在包括所述栅极和所述间隔物的所述半导体衬底上形成层间电介质膜。

    NANOSTRUCTURE COMPOSITE AND METHOD OF PRODUCING THE SAME
    13.
    发明申请
    NANOSTRUCTURE COMPOSITE AND METHOD OF PRODUCING THE SAME 审中-公开
    纳米结构复合材料及其制造方法

    公开(公告)号：US20100255252A1

    公开(公告)日：2010-10-07

    申请号：US12676185

    申请日：2008-09-03

    Applicant: Sang-Hyeob Kim ,  Seung-Sik Park ,  Sang-Woo Kim ,  Gong-Gu Lee ,  Sung-Jin Kim ,  Sunglyul Maeng ,  Sunyoung Lee ,  Hey-Jin Myoung

    Inventor： Sang-Hyeob Kim ,  Seung-Sik Park ,  Sang-Woo Kim ,  Gong-Gu Lee ,  Sung-Jin Kim ,  Sunglyul Maeng ,  Sunyoung Lee ,  Hey-Jin Myoung

    IPC: B82B3/00 ,  C23C16/40

    CPC classification number: H01J9/025 ,  H01J1/304 ,  H01J2201/30469 ,  H01J2329/0455 ,  Y10T428/24355

    Abstract: Provided is a nano structure composite and a method of manufacturing the same. More specifically, a nano structure composite that includes a substrate, a first layer formed of carbon nano structures on the substrate, and a second layer formed of metal oxide nano structures on the first layer, and a method of manufacturing the same are provided. When the nano structure composite according to the present invention is used, a device having a field emission characteristic higher efficiency than a conventional device can be realized, and also, the device can be manufactured at a lower temperature and at a lower pressure. Thus, manufacturing cost can be reduced and a large scale process can be performed.

    Abstract translation: 提供了一种纳米结构复合材料及其制造方法。 更具体地说，提供一种纳米结构复合体及其制造方法，所述纳米结构复合体包括基板，由所述基板上的碳纳米结构形成的第一层和由所述第一层上的金属氧化物纳米结构形成的第二层。 当使用根据本发明的纳米结构复合材料时，可以实现具有比常规器件更高效率的场发射特性的器件，并且还可以在较低温度和较低压力下制造器件。 因此，可以降低制造成本并且可以执行大规模处理。

    Flash memory device and method of forming the device
    14.
    发明授权
    Flash memory device and method of forming the device 失效
    闪存装置及其形成方法

    公开(公告)号：US07767566B2

    公开(公告)日：2010-08-03

    申请号：US11963563

    申请日：2007-12-21

    Applicant: Sung-Jin Kim

    Inventor： Sung-Jin Kim

    IPC: H01L21/00

    CPC classification number: H01L27/115 ,  H01L27/11519

    Abstract: Cell gate patterns including first portions separated from each other with a first distance and second portions separated from each other with a second distance less than the first distance, and spacers are formed both sidewalls of the pair of cell gate patterns. The spacers formed on the sidewalls of the second portions are removed using a mask pattern. Accordingly, it is possible to prevent increase of an aspect ratio of a gap between the second portions with the small distance. Since the spacers formed on the sidewalls of the second portions separated from each other with the small distance are selectively removed, it is possible to minimize the increase of the aspect ratio of the gap between the second portions. Thus, it is possible to solve various problems which are caused due to occurrence of a void.

    Abstract translation: 电池栅极图案包括彼此分离的第一部分，第一距离和第二部分彼此分开，第二距离小于第一距离，并且间隔物形成在该对单元栅极图案的两个侧壁上。 使用掩模图案去除形成在第二部分的侧壁上的间隔物。 因此，可以防止第二部分之间的间隙的纵横比以较小的距离增加。 由于选择性地除去形成在彼此分开的小的距离的第二部分的侧壁上的间隔物，所以可以最小化第二部分之间的间隙的纵横比的增加。 因此，可以解决由于空隙的发生而引起的各种问题。

    Module for manufacturing a display device, method of manufacturing the same, and method of manufacturing a display device using the same
    16.
    发明授权
    Module for manufacturing a display device, method of manufacturing the same, and method of manufacturing a display device using the same 失效
    用于制造显示装置的模块及其制造方法以及使用其的显示装置的制造方法

    公开(公告)号：US07568961B2

    公开(公告)日：2009-08-04

    申请号：US11404208

    申请日：2006-04-14

    Applicant: Sung-Jin Kim

    Inventor： Sung-Jin Kim

    IPC: H01J9/00

    CPC classification number: G02F1/133305 ,  G02F1/133351 ,  H01J9/241 ,  H01J9/261 ,  H01L51/56 ,  H01L2227/326 ,  H01L2251/5338

    Abstract: A module for manufacturing a display device, a method for manufacturing the module, and a method for manufacturing a display device using the module, are provided. The module includes a solid substrate, a first flexible substrate, a second flexible substrate, and a third flexible substrate in one embodiment. The solid substrate has an upper surface and a lower surface facing to the upper surface. The first flexible substrate is on the upper surface of the solid substrate, and the second flexible substrate is on the first flexible substrate and has an opening to receive a flexible display substrate that has a display element. The third flexible substrate is on the lower surface of the solid substrate to prevent a bending of the solid substrate. Advantageously, a malfunction of pixels of the display element is decreased, and the module for manufacturing the display device may be recycled to decrease a manufacturing cost of the display device.

    Abstract translation: 提供一种显示装置的制造用模块，该模块的制造方法以及使用该模块的显示装置的制造方法。 在一个实施例中，该模块包括固体衬底，第一柔性衬底，第二柔性衬底和第三柔性衬底。 固体基板具有面向上表面的上表面和下表面。 第一柔性基板在固体基板的上表面上，第二柔性基板位于第一柔性基板上，并且具有开口以接收具有显示元件的柔性显示基板。 第三柔性基板在固体基板的下表面上，以防止固体基板弯曲。 有利地，显示元件的像素的故障减少，并且用于制造显示装置的模块可以被再循环以降低显示装置的制造成本。

    In-plane switching mode liquid crystal display device and method of fabricating the same
    17.
    发明授权
    In-plane switching mode liquid crystal display device and method of fabricating the same 有权
    面内切换模式液晶显示装置及其制造方法

    公开(公告)号：US07542119B2

    公开(公告)日：2009-06-02

    申请号：US11246234

    申请日：2005-10-11

    Applicant: Jeong-Hoon Ko ,  Sung-Jin Kim

    Inventor： Jeong-Hoon Ko ,  Sung-Jin Kim

    IPC: G02F1/1343

    CPC classification number: G02F1/134363 ,  G02F2201/124

    Abstract: An array substrate for an in-plane switching mode liquid crystal display devices includes: a substrate; a gate line and a data line on the substrate, the gate line crossing the data line to define a pixel region; a common line parallel to the gate line; a thin film transistor connected to the gate line and the data line; a plurality of common electrodes extending from the common line, and a plurality of pixel electrodes alternating with the plurality of common electrodes, wherein a gap distance is defined as a width of a block by the adjacent common and pixel electrode in the pixel region, and at least one gap distance is different from the other gap distances.

    Abstract translation: 面内切换模式液晶显示装置的阵列基板包括：基板; 栅极线和数据线，栅极线与数据线交叉以限定像素区域; 与栅极线平行的公共线; 连接到栅极线和数据线的薄膜晶体管; 从公共线延伸的多个公共电极和与多个公共电极交替的多个像素电极，其中间隙距离被定义为像素区域中的相邻公共和像素电极的块宽度，以及 至少一个间隙距离与其他间隙距离不同。

    Thin film transistor array panel and manufacturing method thereof
    18.
    发明授权
    Thin film transistor array panel and manufacturing method thereof 失效
    薄膜晶体管阵列面板及其制造方法

    公开(公告)号：US07527992B2

    公开(公告)日：2009-05-05

    申请号：US11260017

    申请日：2005-10-26

    Applicant: Je-Hun Lee ,  Sung-Jin Kim ,  Hee-Joon Kim ,  Chang-Oh Jeong

    Inventor： Je-Hun Lee ,  Sung-Jin Kim ,  Hee-Joon Kim ,  Chang-Oh Jeong

    IPC: H01L21/84

    CPC classification number: G02F1/13439 ,  G02F1/13458 ,  H01L27/12 ,  H01L27/124 ,  H01L29/458 ,  H01L29/4908

    Abstract: A thin film transistor array panel is provided, which includes a substrate, a plurality of gate line formed on the substrate, a plurality of common electrodes having a transparent conductive layer on the substrate, a gate insulating layer covering the gate lines and the common electrodes, a plurality of semiconductor layers formed on the gate insulating layer, a plurality of data lines including a plurality of source electrodes and formed on the semiconductor layer and the gate insulating layer, a plurality of drain electrodes formed on the semiconductor layer and the gate insulating layer, and a plurality of pixel electrodes overlapping the common electrodes and connected to the drain electrodes. Because the common electrodes are made of ITON, IZON, or a-ITON, or a double layer of ITO/ITON, IZO/IZON, or a-a-ITO/a-ITON, when H2 or SiH4 are injected to form a silicon nitride (SiNX) layer on the common electrodes, the opaque metal Sn or Zn in which the metal component is reduced in the IZO, ITO, or a-ITO is not produced on the surfaces of the common electrode.

    Abstract translation: 提供薄膜晶体管阵列面板，其包括基板，形成在基板上的多个栅极线，在基板上具有透明导电层的多个公共电极，覆盖栅极线和公共电极的栅极绝缘层 形成在所述栅极绝缘层上的多个半导体层，形成在所述半导体层和所述栅极绝缘层上的多个源极电极的多条数据线，形成在所述半导体层上的多个漏电极和所述栅极绝缘体 并且与公共电极重叠并连接到漏电极的多个像素电极。 由于公共电极由ITON，IZON或者-IONON制成，或者是将双重层的ITO / ITON，IZO / IZON或者a-ITO / a-ITON，当注入H 2或SiH 4以形成氮化硅时 SiNX）层，在公共电极的表面上不产生在IZO，ITO或ITO中还原金属成分的不透明金属Sn或Zn。

    FLASH MEMORY DEVICE AND METHOD OF FORMING THE DEVICE
    20.
    发明申请
    FLASH MEMORY DEVICE AND METHOD OF FORMING THE DEVICE 失效
    闪存存储器件和形成器件的方法

    公开(公告)号：US20080157180A1

    公开(公告)日：2008-07-03

    申请号：US11963563

    申请日：2007-12-21

    Applicant: Sung-Jin Kim

    Inventor： Sung-Jin Kim

    IPC: H01L29/423 ,  H01L21/28

    CPC classification number: H01L27/115 ,  H01L27/11519

    Abstract: Cell gate patterns including first portions separated from each other with a first distance and second portions separated from each other with a second distance less than the first distance, and spacers are formed both sidewalls of the pair of cell gate patterns. The spacers formed on the sidewalls of the second portions are removed using a mask pattern. Accordingly, it is possible to prevent increase of an aspect ratio of a gap between the second portions with the small distance. Since the spacers formed on the sidewalls of the second portions separated from each other with the small distance are selectively removed, it is possible to minimize the increase of the aspect ratio of the gap between the second portions. Thus, it is possible to solve various problems which are caused due to occurrence of a void.

    Abstract translation: 电池栅极图案包括彼此分离的第一部分，第一距离和第二部分彼此分开，第二距离小于第一距离，并且间隔物形成在该对单元栅极图案的两个侧壁上。 使用掩模图案去除形成在第二部分的侧壁上的间隔物。 因此，可以防止第二部分之间的间隙的纵横比以较小的距离增加。 由于选择性地除去形成在彼此分开的小的距离的第二部分的侧壁上的间隔物，所以可以最小化第二部分之间的间隙的纵横比的增加。 因此，可以解决由于空隙的发生而引起的各种问题。

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