公开(公告)号：US20230208675A1

公开(公告)日：2023-06-29

申请号：US18117511

申请日：2023-03-06

Applicant: Texas Instruments Incorporated

Inventor： Raghu Ganesan ,  Saravanakkumar Radhakrishnan ,  Gaurav Aggarwal

IPC: H04L12/40 ,  H04L12/64 ,  H04L25/03 ,  H04L43/0823

CPC classification number: H04L12/40039 ,  H04L12/6418 ,  H04L25/03267 ,  H04L43/0823 ,  H04L2012/6467 ,  H04L2027/0069

Abstract: A receiver circuit includes a feedback loop including a device. The receiver circuit also includes a register and a sequencer. The sequencer is configured to, responsive to an error signal being below a threshold value, cause the register to store a value indicative of the state of the feedback loop. The sequencer is also configured to cause the feedback loop to transition to a lower power state, and, responsive to a detected wake-up event, cause the previously stored value indicative of the state of the feedback loop to be loaded from the register into the device and enable the feedback loop.

公开(公告)号：US20230136070A1

公开(公告)日：2023-05-04

申请号：US17729654

申请日：2022-04-26

Applicant: Texas Instruments Incorporated

Inventor： Raghu Ganesan ,  Saravanakkumar Radhakrishnan

IPC: H04L7/00

Abstract: Methods, apparatus, and systems to synchronize Ethernet signals are disclosed. An example apparatus includes slicer circuitry having an input coupled to interface circuitry and having an output, the slicer circuitry configured to receive an analog signal corresponding to a first Analog to Digital Converter (ADC) clock in a plurality of ADC clocks and operable to determine symbols based on the analog signal; logic circuitry to determine whether there is a symbol transition in the symbols; timing error detector circuitry to update an error value in response to the determination that there is a symbol transition; timing loop circuitry to determine a frequency of voltage oscillations based on at least the error value; and phase interpolator circuitry to change a plurality of phase parameters corresponding to the plurality of ADC clocks at a rate given by the frequency of voltage oscillations.

公开(公告)号：US11601302B2

公开(公告)日：2023-03-07

申请号：US17082208

申请日：2020-10-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Raghu Ganesan ,  Saravanakkumar Radhakrishnan ,  Gaurav Aggarwal

IPC: H04L25/03 ,  H04L27/00 ,  H04L12/40 ,  H04L12/64 ,  H04L43/0823

Abstract: A receiver circuit includes a feedback loop including a device. The receiver circuit also includes a register and a sequencer. The sequencer is configured to, responsive to an error signal being below a threshold value, cause the register to store a value indicative of the state of the feedback loop. The sequencer is also configured to cause the feedback loop to transition to a lower power state, and, responsive to a detected wake-up event, cause the previously stored value indicative of the state of the feedback loop to be loaded from the register into the device and enable the feedback loop.

公开(公告)号：US11469785B2

公开(公告)日：2022-10-11

申请号：US17200060

申请日：2021-03-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Raghu Ganesan ,  Gaurav Aggarwal ,  Rahul Koppisetti ,  Rallabandi V Lakshmi Annapurna ,  Saravanakkumar Radhakrishnan ,  Kalpesh Laxmanbhai Rajai

IPC: H04B1/10 ,  H04B1/12 ,  H04B1/16 ,  H03M1/00 ,  H03M1/06 ,  H03M1/50

Abstract: A receiver circuit includes an ADC, a processing channel, and an interference detection path. The processing channel is configured to process data samples provided by the ADC, and includes a notch filter. The interference detection path is configured to detect interference in the data samples, and includes a slicer, a slicer error circuit, and an interference detection circuit. The slicer is configured to slice input of the notch filter. The slicer error circuit is configured to compute an error of the slicer. The interference detection circuit configured to detect an interference signal in the error of the slicer, and set the notch filter to attenuate the interference signal.