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    Method For Fabricating Buried Capacitor Structure
    11.
    发明申请
    Method For Fabricating Buried Capacitor Structure 有权
    制造掩埋电容器结构的方法

    公开(公告)号：US20100307666A1

    公开(公告)日：2010-12-09

    申请号：US12479811

    申请日：2009-06-07

    Applicant: Chien-Wei Chang ,  Ting-Hao Lin ,  Ya-Hsiang Chen ,  Yu-Te Lu

    Inventor： Chien-Wei Chang ,  Ting-Hao Lin ,  Ya-Hsiang Chen ,  Yu-Te Lu

    IPC: B32B37/00

    CPC classification number: B32B37/02 ,  B32B38/06 ,  B32B2038/047 ,  B32B2457/08 ,  B32B2457/16 ,  H01G4/236 ,  H01G4/33 ,  H05K1/162 ,  H05K3/4602 ,  H05K2201/09236 ,  H05K2201/09509 ,  H05K2203/1461

    Abstract: A method for fabricating a buried capacitor structure includes: laminating a first dielectric layer having a capacitor embedded therein with a second dielectric layer to bury the capacitor therebetween; forming a first circuit pattern on a first metal layer of the first dielectric layer and a second circuit pattern on a second metal layer of the second dielectric layer; depositing a first insulating layer and a second insulating layer on the first metal layer and the second metal layer, respectively; electrically connecting a positive electrode end and a negative electrode end of the capacitor to the second metal layer by a positive through-hole and a negative through-hole, thereby manufacturing the buried capacitor structure.

    Abstract translation: 一种埋入式电容器结构的制造方法，其特征在于：将具有嵌入其中的电容器的第一电介质层与第二电介质层层叠， 在所述第一介电层的第一金属层上形成第一电路图案，在所述第二介电层的第二金属层上形成第二电路图案; 分别在第一金属层和第二金属层上沉积第一绝缘层和第二绝缘层; 通过正通孔和负通孔将电容器的正极端子和负极端子电连接到第二金属层，从而制造埋入式电容器结构。

    Non-Plating Line Plating Method Using Current Transmitted From Ball Side
    12.
    发明申请
    Non-Plating Line Plating Method Using Current Transmitted From Ball Side 审中-公开
    使用从球侧传输的电流的非电镀线电镀方法

    公开(公告)号：US20100075497A1

    公开(公告)日：2010-03-25

    申请号：US12236493

    申请日：2008-09-23

    Applicant: Chien-Wei Chang ,  Ting-Hao Lin ,  Yu-Te Lu

    Inventor： Chien-Wei Chang ,  Ting-Hao Lin ,  Yu-Te Lu

    IPC: H01L21/44 ,  H01L21/288

    CPC classification number: H05K3/242 ,  H05K3/42 ,  H05K2201/0352 ,  H05K2203/1476 ,  H05K2203/1581

    Abstract: A non-plating line (NPL) plating method is provided. The NPL plating method is featured in that at first it forms a circuit layer on a bump side only, and therefore a plating current can be transmitted via a plating metal layer on a ball side to the circuit layer (enclosed by an insulation layer, e.g., a solder resist or a photoresist) on the bump side, and thus forming a protection layer, e.g., plating gold, on the plating metal layer on the circuit layer and the ball side. In such a way, the plating gold is formed after the insulation layer, so that there won't be any plating gold existed beneath the insulation layer of the bump side (connected with dies). Hence, the insulation layer can be prevented from dropping off from the protection layer, i.e., the plating gold, and thus the reliability of the products can be improved.

    Abstract translation: 提供非电镀线（NPL）电镀方法。 NPL镀覆方法的特征在于，它首先仅在凸块侧形成电路层，因此电镀电流可以通过球侧的电镀金属层传输到电路层（由绝缘层包围，例如 ，阻焊剂或光致抗蚀剂），从而在电路层和球侧的电镀金属层上形成保护层，例如镀金。 以这种方式，在绝缘层之后形成电镀金，使得在凸起侧（与模具连接）的绝缘层下方不存在镀金。 因此，可以防止绝缘层从保护层即电镀金脱落，从而可以提高产品的可靠性。

    COMPOSITE CIRCUIT BOARD AND METHOD FOR MANUFACTURING THE SAME
    14.
    发明申请
    COMPOSITE CIRCUIT BOARD AND METHOD FOR MANUFACTURING THE SAME 失效
    复合电路板及其制造方法

    公开(公告)号：US20070144768A1

    公开(公告)日：2007-06-28

    申请号：US11319998

    申请日：2005-12-27

    Applicant: Ting-Hao Lin ,  Chung-Yuan Chen

    Inventor： Ting-Hao Lin ,  Chung-Yuan Chen

    IPC: H05K1/03

    CPC classification number: H05K3/4691 ,  H05K3/0052 ,  H05K3/0097 ,  H05K3/4688 ,  H05K2203/065 ,  H05K2203/167 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49155

    Abstract: A composite circuit board comprises multiple soft panels evenly mounted on a rigid panel. The soft panels are positioned on the rigid panel in proper alignment via locating pins on the rigid panel and corresponding holes in the soft panels. The soft panels are securely bonded to the rigid panel to form the composite circuit boards. The smaller size of the soft panels minimizes the alignment problems caused by the different heat expansion rates of the soft panel and the rigid panel.

    Abstract translation: 复合电路板包括均匀地安装在刚性面板上的多个软面板。 柔性面板通过刚性面板上的定位销和软面板中的相应孔定位在刚性面板上，以适当对准。 软面板牢固地结合到刚性面板上以形成复合电路板。 较小尺寸的软面板使由柔性面板和刚性面板的不同热膨胀率引起的对准问题最小化。

    Solid tape automated bonding packaging method
    15.
    发明授权
    Solid tape automated bonding packaging method 失效
    实心胶带自动粘接包装方法

    公开(公告)号：US5763294A

    公开(公告)日：1998-06-09

    申请号：US856966

    申请日：1997-05-15

    Applicant: Ting-Hao Lin

    Inventor： Ting-Hao Lin

    IPC: H01L21/60

    CPC classification number: H01L24/86 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/181

    Abstract: A solid tape automated bonding method includes steps of: applying a pattern of a first dry film on a first portion of a copper plate; forming wiring; forming bumps; removing dry film and exposing the wiring and the bumps; selectively laminating an insulator layer onto portions of the exposed copper plate and the wiring; laminating a metal layer on the insulator layer; applying glue on the metal layer, the bumps, and respective exposed portions of the wiring and the copper plate; etching the copper plate thus exposing one side of the wiring as ball pads and exposing one side of the insulator layer; coating solder resist on the exposed bottom side of the insulator layer; removing the glue; attaching a die against the bumps; applying mold compound onto the die so as to fix the die in place; and attaching solder balls onto the ball pads. This method provides relatively high density of wiring and simplification in manufacturing.

    Abstract translation: 固体胶带自动接合方法包括以下步骤：将第一干膜的图案施加在铜板的第一部分上; 形成布线 形成凸块; 去除干膜并暴露布线和凸块; 选择性地将绝缘体层压到暴露的铜板和布线的部分上; 在绝缘体层上层压金属层; 在金属层，凸块以及布线和铜板的各自的暴露部分上施加胶水; 蚀刻铜板，从而将布线的一侧作为球垫露出并暴露绝缘体层的一侧; 在绝缘体层的暴露的底侧涂覆阻焊剂; 去除胶水; 将模具贴靠在凸起上; 将模具化合物涂覆在模具上，以将模具固定就位; 并将焊球附着到球垫上。 该方法提供相对较高的布线密度和制造简化。

    Manufacturing Method Of A Semiconductor Load Board
    17.
    发明申请
    Manufacturing Method Of A Semiconductor Load Board 有权
    半导体负载板的制造方法

    公开(公告)号：US20120231621A1

    公开(公告)日：2012-09-13

    申请号：US13043463

    申请日：2011-03-09

    Applicant: Chien-Wei Chang ,  Ting-Hao Lin ,  Ya-Hsiang Chen

    Inventor： Chien-Wei Chang ,  Ting-Hao Lin ,  Ya-Hsiang Chen

    IPC: H01L21/28

    CPC classification number: H01L24/13 ,  H01L21/4853 ,  H01L23/49811 ,  H01L24/11 ,  H01L2224/1147 ,  H01L2224/11903 ,  H01L2224/13022 ,  H01L2224/13076 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13611 ,  H01L2224/13655 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01079 ,  H01L2924/00

    Abstract: A manufacturing method of a semiconductor load board is disclosed. The manufacturing method includes a first conductive layer forming step, a first patterning step, a dielectric layer forming step, a drilling step, a second conductive layer forming step, a second patterning step or a two-times patterning step, and a solder connecting step. In a second patterning step or a two-times patterning step, a solder pads is formed in the opening of the dielectric layer, wherein each solder pad has a height higher than the height of the dielectric, and the width of each solder pad is equal to or smaller than the maximum width of the opening, such that wider intervals are provided in the same area and the problems of short circuit failure and electrical interference can be reduced.

    Abstract translation: 公开了一种半导体负载板的制造方法。 该制造方法包括第一导电层形成步骤，第一图案化步骤，介电层形成步骤，钻孔步骤，第二导电层形成步骤，第二图案化步骤或两次图案化步骤，以及焊料连接步骤 。 在第二图案化步骤或两次图案化步骤中，在电介质层的开口中形成焊盘，其中每个焊盘的高度高于电介质的高度，并且每个焊垫的宽度相等 达到或小于开口的最大宽度，使得在相同的区域中设置更宽的间隔，并且可以减少短路故障和电气干扰的问题。

    Method for fabricating buried capacitor structure
    18.
    发明授权
    Method for fabricating buried capacitor structure 有权
    掩埋电容器结构的制造方法

    公开(公告)号：US07871892B2

    公开(公告)日：2011-01-18

    申请号：US12479811

    申请日：2009-06-07

    Applicant: Chien-Wei Chang ,  Ting-Hao Lin ,  Ya-Hsiang Chen ,  Yu-Te Lu

    Inventor： Chien-Wei Chang ,  Ting-Hao Lin ,  Ya-Hsiang Chen ,  Yu-Te Lu

    IPC: H01L21/20

    CPC classification number: B32B37/02 ,  B32B38/06 ,  B32B2038/047 ,  B32B2457/08 ,  B32B2457/16 ,  H01G4/236 ,  H01G4/33 ,  H05K1/162 ,  H05K3/4602 ,  H05K2201/09236 ,  H05K2201/09509 ,  H05K2203/1461

    Abstract: A method for fabricating a buried capacitor structure includes: laminating a first dielectric layer having a capacitor embedded therein with a second dielectric layer to bury the capacitor therebetween; forming a first circuit pattern on a first metal layer of the first dielectric layer and a second circuit pattern on a second metal layer of the second dielectric layer; depositing a first insulating layer and a second insulating layer on the first metal layer and the second metal layer, respectively; electrically connecting a positive electrode end and a negative electrode end of the capacitor to the second metal layer by a positive through-hole and a negative through-hole, thereby manufacturing the buried capacitor structure.

    Abstract translation: 一种埋入式电容器结构的制造方法，其特征在于：将具有嵌入其中的电容器的第一电介质层与第二电介质层层叠， 在所述第一介电层的第一金属层上形成第一电路图案，在所述第二介电层的第二金属层上形成第二电路图案; 分别在第一金属层和第二金属层上沉积第一绝缘层和第二绝缘层; 通过正通孔和负通孔将电容器的正极端子和负极端子电连接到第二金属层，从而制造埋入式电容器结构。

    Manufacturing method of non-etched circuit board
    19.
    发明授权
    Manufacturing method of non-etched circuit board 有权
    非蚀刻电路板的制造方法

    公开(公告)号：US07807034B2

    公开(公告)日：2010-10-05

    申请号：US11734274

    申请日：2007-04-12

    Applicant: Ting-Hao Lin

    Inventor： Ting-Hao Lin

    IPC: C25D5/02

    CPC classification number: H05K3/423 ,  H05K3/0035 ,  H05K3/025 ,  H05K3/205 ,  H05K3/242 ,  H05K3/382 ,  H05K3/421 ,  H05K2201/09563 ,  H05K2203/0376 ,  H05K2203/0384 ,  H05K2203/0554 ,  H05K2203/1152

    Abstract: A manufacturing method of a non-etched circuit board is disclosed herein, which employs a metal substrate having a metal barrier layer and an electroplated copper layer to transmit an electrical current to form a circuit layer. A patterned photoresist layer is formed on the electroplated copper layer to define the location of the circuit layer and form circuits or conductive via on the board by electroplating. An electroplated nickel layer or an electroplated gold layer is further formed on the circuit layer for protecting the circuits and improving the fine line capability. During or after the process, the metal substrate, the metal barrier layer, and the electroplated copper layer are removed to enlarge the wiring space, so that a high-density circuit board can be obtained.

    Abstract translation: 本文公开了一种未蚀刻电路板的制造方法，其采用具有金属阻挡层和电镀铜层的金属基板来传输电流以形成电路层。 在电镀铜层上形成图案化的光致抗蚀剂层以限定电路层的位置，并通过电镀在电路板上形成电路或导电通孔。 在电路层上进一步形成电镀镍层或电镀金层，以保护电路并提高细线能力。 在处理过程中或之后，去除金属基板，金属阻挡层和电镀铜层以扩大布线空间，从而可以获得高密度电路板。

    Method Of Selectively Plating Without Plating Lines
    20.
    发明申请
    Method Of Selectively Plating Without Plating Lines 审中-公开
    选择电镀方法，无电镀线

    公开(公告)号：US20100075495A1

    公开(公告)日：2010-03-25

    申请号：US12237402

    申请日：2008-09-25

    Applicant: Chien-Wei Chang ,  Ting-Hao Lin ,  Yu-Te Lu

    Inventor： Chien-Wei Chang ,  Ting-Hao Lin ,  Yu-Te Lu

    IPC: H01L21/44

    CPC classification number: H05K3/205 ,  H05K3/244 ,  H05K3/4647 ,  H05K2203/0361

    Abstract: A method of selectively plating without plating lines is provided. The method employs a loading plate having a metalized temporary conductive layer. The loading plate and the temporary conductive layer are adapted for transmitting a plating current. A patterning photoresist layer is accorded for selectively and sequentially plating a separating metal layer, a plating protection layer, and a connection pad layer on to the temporary conductive layer. Then, the loading plate is further used for supplying current to form other circuit layers by a pressing lamination process. And when the plate process is completed or it is not need to plate, the loading plate and the temporary conductive layer can be removed, for further completing for example the solder mask process, and thus achieving the objective of plating without plating lines.

    Abstract translation: 提供了一种选择性地镀覆电镀线的方法。 该方法采用具有金属化的临时导电层的装载板。 装载板和临时导电层适于传输电镀电流。 符合图案化光刻胶层的选择性和顺序地将分离金属层，电镀保护层和连接焊盘层电镀到临时导电层上。 然后，通过加压层压工艺，装载板还用于供给电流以形成其它电路层。 并且，当平板工艺完成或不需要平板化时，可以去除装载板和临时导电层，以进一步完成例如焊接掩模工艺，从而实现不镀覆线的电镀目的。

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