公开(公告)号：US20100170088A1

公开(公告)日：2010-07-08

申请号：US12725460

申请日：2010-03-17

Applicant: Chien-Wei Chang ,  Ting-Hao Lin ,  Jen-Fang Chang ,  Yu-Te Lu ,  Chia-Chi Lo

Inventor： Chien-Wei Chang ,  Ting-Hao Lin ,  Jen-Fang Chang ,  Yu-Te Lu ,  Chia-Chi Lo

IPC: H05K3/10

CPC classification number: H05K3/4602 ,  H05K3/108 ,  H05K3/427 ,  H05K2201/0347 ,  H05K2201/09536 ,  H05K2201/0959 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49165

Abstract: Structure and method of making a board having plating though hole (PTH) core layer substrate and stacked multiple layers of blind vias. More stacking layers of blind vias than conventional methods can be achieved. The fabrication method of the board having high-density core layer includes the following: after the making of the PTH, the filling material filled inside the PTH of the core layer is partially removed until the PTH has reached an appropriate flattened depression using etching; then image transfer and pattern plating are performed to fill and to level the depression portion up to a desired thickness to form a copper pad (overplating) as the core layer substrate is forming a circuit layer; finally using electroless copper deposition and the pattern plating to make the product.

Abstract translation: 制造具有电镀通孔（PTH）芯层衬底和层叠多层盲孔的板的结构和方法。 可以实现比常规方法更多的盲孔堆叠层。 具有高密度芯层的板的制造方法包括以下：在制造PTH之后，填充在芯层的PTH内部的填充材料被部分地去除，直到PTH已经通过蚀刻达到适当的平坦凹陷; 然后进行图像转印和图案电镀，以在芯层基板正在形成电路层时填充并使凹陷部分达到所需厚度以形成铜焊盘（过镀层）; 最后使用无电镀铜和图案电镀制成产品。

公开(公告)号：US20090308527A1

公开(公告)日：2009-12-17

申请号：US12137553

申请日：2008-06-12

Applicant: Chien-Wei Chang ,  Ting-Hao Lin ,  Bo-Yu Tseng

Inventor： Chien-Wei Chang ,  Ting-Hao Lin ,  Bo-Yu Tseng

IPC: B32B38/10

CPC classification number: H05K3/427 ,  B32B37/025 ,  B32B38/10 ,  B32B2038/0016 ,  B32B2305/076 ,  B32B2311/00 ,  B32B2457/08 ,  C22C1/002 ,  H05K3/025 ,  H05K3/108 ,  H05K3/382 ,  H05K2201/0347 ,  H05K2201/0959 ,  H05K2203/0361 ,  H05K2203/0384

Abstract: A method for fabricating a circuit trace on a core board having a buried hole is provided. The method includes: providing a carrier plate having a detachable metal layer, an etching barrier layer, and a metal layer sequentially stacked thereon; roughening the metal layer which can be completely roughened; laminating the bonded metal layer, the etching barrier layer, the detachable metal layer and the carrier plate onto a dielectric, wherein the metal layer faces and contacts with the dielectric; and then removing the carrier plate therefrom. As such, even if the dielectric is difficult to be completely roughened, the roughened metal layer can enhance the bondability between the metal layer and the dielectric. The metal layer is processed to become the circuit trace later.

Abstract translation: 提供了一种用于在具有掩埋孔的芯板上制造电路迹线的方法。 该方法包括：提供具有可分离的金属层，蚀刻阻挡层和顺序堆叠在其上的金属层的载体板; 使可以完全粗糙化的金属层变粗糙; 将接合的金属层，蚀刻阻挡层，可拆卸金属层和载体板层压到电介质上，其中金属层面对并与电介质接触; 然后从其移除载体板。 因此，即使电介质难以完全粗糙化，粗糙化的金属层也可以提高金属层与电介质的结合性。 金属层后处理成电路迹线。

公开(公告)号：US20080251386A1

公开(公告)日：2008-10-16

申请号：US11734274

申请日：2007-04-12

Applicant: Ting-Hao Lin

Inventor： Ting-Hao Lin

IPC: C25D5/02

CPC classification number: H05K3/423 ,  H05K3/0035 ,  H05K3/025 ,  H05K3/205 ,  H05K3/242 ,  H05K3/382 ,  H05K3/421 ,  H05K2201/09563 ,  H05K2203/0376 ,  H05K2203/0384 ,  H05K2203/0554 ,  H05K2203/1152

Abstract: A manufacturing method of a non-etched circuit board is disclosed herein, which employs a metal substrate having a metal barrier layer and an electroplated copper layer to transmit an electrical current to form a circuit layer. A patterned photoresist layer is formed on the electroplated copper layer to define the location of the circuit layer and form circuits or conductive via on the board by electroplating. An electroplated nickel layer or an electroplated gold layer is further formed on the circuit layer for protecting the circuits and improving the fine line capability. During or after the process, the metal substrate, the metal barrier layer, and the electroplated copper layer are removed to enlarge the wiring space, so that a high-density circuit board can be obtained.

Abstract translation: 本文公开了一种未蚀刻电路板的制造方法，其采用具有金属阻挡层和电镀铜层的金属基板来传输电流以形成电路层。 在电镀铜层上形成图案化的光致抗蚀剂层以限定电路层的位置，并通过电镀在电路板上形成电路或导电通孔。 在电路层上进一步形成电镀镍层或电镀金层，以保护电路并提高细线能力。 在处理过程中或之后，去除金属基板，金属阻挡层和电镀铜层以扩大布线空间，从而可以获得高密度电路板。

公开(公告)号：US20070148970A1

公开(公告)日：2007-06-28

申请号：US11319874

申请日：2005-12-27

Applicant: Ting-Hao Lin ,  Chih-Wei Lee

Inventor： Ting-Hao Lin ,  Chih-Wei Lee

IPC: H01L21/44

CPC classification number: H05K3/427 ,  H05K3/062 ,  H05K3/243 ,  H05K2201/09545

Abstract: A method of fabricating circuitry without conductive circles has steps of providing a plate with multiple apertures defined therein, the plate and inner walls of the apertures are coated with a copper layer; the copper layers are coated with a photoresist layer, which is then covered with a protective film; partly removing the photoresist layer at the apertures; removing the protective film to expose the photoresist layer; electroplating the inner walls of the apertures with copper; exposing and developing the photoresist layers; and finally, etching the copper layers to form a circuit pattern without any conductive circles.

Abstract translation: 制造没有导电圆的电路的方法具有提供其中限定有多个孔的板的步骤，所述孔的板和内壁涂覆有铜层; 铜层被涂覆有光致抗蚀剂层，然后用保护膜覆盖; 部分地在孔处除去光致抗蚀剂层; 去除保护膜以暴露光致抗蚀剂层; 用铜电镀孔的内壁; 曝光和显影光刻胶层; 最后，蚀刻铜层以形成没有任何导电圆的电路图案。

公开(公告)号：US07234230B1

公开(公告)日：2007-06-26

申请号：US11319998

申请日：2005-12-27

Applicant: Ting-Hao Lin ,  Chung-Yuan Chen

Inventor： Ting-Hao Lin ,  Chung-Yuan Chen

IPC: H01R43/00

CPC classification number: H05K3/4691 ,  H05K3/0052 ,  H05K3/0097 ,  H05K3/4688 ,  H05K2203/065 ,  H05K2203/167 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49155

Abstract: A composite circuit board comprises multiple soft panels evenly mounted on a rigid panel. The soft panels are positioned on the rigid panel in proper alignment via locating pins on the rigid panel and corresponding holes in the soft panels. The soft panels are securely bonded to the rigid panel to form the composite circuit boards. The smaller size of the soft panels minimizes the alignment problems caused by the different heat expansion rates of the soft panel and the rigid panel.

Abstract translation: 复合电路板包括均匀地安装在刚性面板上的多个软面板。 柔性面板通过刚性面板上的定位销和软面板中的相应孔定位在刚性面板上，以适当对准。 软面板牢固地结合到刚性面板上以形成复合电路板。 较小尺寸的软面板使由柔性面板和刚性面板的不同热膨胀率引起的对准问题最小化。

公开(公告)号：US06830496B2

公开(公告)日：2004-12-14

申请号：US10349242

申请日：2003-01-22

Applicant: Ting-Hao Lin ,  Li-Wei Kuo ,  Ching-Lin Chang

Inventor： Ting-Hao Lin ,  Li-Wei Kuo ,  Ching-Lin Chang

IPC: H01J900

CPC classification number: H01L33/62 ,  H01L25/0753 ,  H01L33/641 ,  H01L33/647 ,  H01L2224/48091 ,  H01L2924/12041 ,  H01L2924/00014

Abstract: A light emitting diode device comprises a copper substrate having multiple light emitting regions, multiple dies and encapsulation. Each light emitting region has a die pad and at least one electrode connected together and encapsulant covering the light emitting region. The dies are respectively mounted on the die pads and are wire bonded to the corresponding electrode or electrodes. A step defining a gap is applied to the substrate to form multiple light emitting regions, and each light emitting region has a die pad and electrodes. Therefore, the present invention can simplify the steps for fabricating die pad and electrodes to increase the production rate of LED devices or LED display modules.

Abstract translation: 发光二极管器件包括具有多个发光区域的铜衬底，多个管芯和封装。 每个发光区域具有管芯焊盘和连接在一起的至少一个电极和覆盖发光区域的密封剂。 模具分别安装在芯片焊盘上，并且引线键合到相应的电极或电极。 对衬底施加限定间隙的步骤以形成多个发光区域，并且每个发光区域具有管芯焊盘和电极。 因此，本发明可以简化制造管芯焊盘和电极的步骤，以增加LED器件或LED显示模块的生产率。

公开(公告)号：US20130233602A1

公开(公告)日：2013-09-12

申请号：US13416158

申请日：2012-03-09

Applicant: Ting-Hao Lin ,  Yu-Hui Wu

Inventor： Ting-Hao Lin ,  Yu-Hui Wu

IPC: H05K1/09

CPC classification number: H05K3/243 ,  H01L2224/13111 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/81444 ,  H01L2224/85444 ,  H05K3/24 ,  H05K2201/0341 ,  H01L2924/00014

Abstract: A surface treatment structure formed on a circuit pattern on a printed circuit board is provided, which includes a first gold layer, a palladium layer, and a second gold layer stacked from bottom to top, respectively, or includes a palladium layer, and a second gold layer stacked from bottom to top, respectively. The palladium layer is used to prevent the diffusion of the copper ions from the circuit pattern. Only a thin surface treatment structure of the circuit pattern of the present invention is required to achieve excellent wire bonding, so that the overall thickness is reduced, and the manufacture cost is also reduced. Furthermore, the uniformness of palladium is better than that of nickel, and thereby the surface treatment structure of the circuit pattern of the present invention is suitably used for manufacturing the fine-line circuits, thereby having a wider industrial applicability.

Abstract translation: 提供了形成在印刷电路板上的电路图案上的表面处理结构，其包括分别从底部至顶部堆叠的第一金层，钯层和第二金层，或包括钯层，第二金层 金层分别从底部到顶部堆叠。 钯层用于防止铜离子从电路图案扩散。 需要本发明的电路图形的薄的表面处理结构来实现优良的引线接合，从而减小总体厚度，并且制造成本也降低。 此外，钯的均匀性优于镍，因此本发明的电路图案的表面处理结构适用于制造细线电路，从而具有更广的工业实用性。

公开(公告)号：US20120228011A1

公开(公告)日：2012-09-13

申请号：US13043462

申请日：2011-03-09

Applicant: Chien-Wei Chang ,  Ting-Hao Lin ,  Ya-Hsiang Chen

Inventor： Chien-Wei Chang ,  Ting-Hao Lin ,  Ya-Hsiang Chen

IPC: H05K1/09 ,  H05K1/00

CPC classification number: H01L23/49816 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13076 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014 ,  H05K3/4007 ,  H05K2201/0367 ,  H01L2224/05552

Abstract: Disclosed is a semiconductor load board, including a substrate, a plurality of connection pads, a patterned circuit layer, a dielectric layer, a plurality of solder pads, and a plurality of solders. The connection pads and the patterned circuit layer are located on the substrate. The dielectric layer is formed on the substrate, the connection pads and the patterned circuit layer, and has a plurality of openings corresponding to the plurality of connection pads. The solder pads are formed in the openings, and the width of the solder pads is smaller than or equals to the maximum width of the openings of the dielectric layer, and a protruding portion which has a width smaller than the minimum width of the openings of the dielectric layer can also be formed, such that the problems of short-circuit failure and electrical interference can be reduced.

Abstract translation: 公开了一种半导体负载板，包括基板，多个连接焊盘，图案化电路层，电介质层，多个焊盘和多个焊料。 连接焊盘和图案化电路层位于衬底上。 介电层形成在基板上，连接焊盘和图案化电路层上，并且具有对应于多个连接焊盘的多个开口。 焊盘形成在开口中，并且焊盘的宽度小于或等于电介质层的开口的最大宽度，并且宽度小于开口的最小宽度的突出部分 还可以形成电介质层，从而可以减少短路故障和电气干扰的问题。

公开(公告)号：US08083954B2

公开(公告)日：2011-12-27

申请号：US12131932

申请日：2008-06-03

Applicant: Chien-Wei Chang ,  Ting-Hao Lin ,  Yu-Te Lu

Inventor： Chien-Wei Chang ,  Ting-Hao Lin ,  Yu-Te Lu

IPC: H01B13/00

CPC classification number: B32B37/226 ,  B32B38/06 ,  B32B2305/342 ,  B32B2457/08 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/8203 ,  H01L2224/83005 ,  H01L2224/83132 ,  H05K1/023 ,  H05K1/185 ,  H05K1/188 ,  H05K3/025 ,  H05K2201/0355 ,  H05K2201/10636 ,  H05K2203/063 ,  Y02P70/611

Abstract: A method for fabricating a component-embedded PCB includes: providing a carrier plate having a plating metal layer plated thereon; disposing an electronic component on the plating metal layer of the carrier plate; laminating a metal layer onto the plating metal layer having the electronic component disposed thereon and the carrier plate by a dielectric film; removing the carrier plate and exposing the plating metal layer; and patterning at least one of the metal layer and the plating metal layer to be a circuit layer.

Abstract translation: 一种用于制造部件嵌入式PCB的方法包括：提供其上镀有电镀金属层的载体板; 将电子部件设置在载体板的电镀金属层上; 通过电介质膜将金属层层叠在其上设置有电子部件的电镀金属层和载体板上; 移除载体板并暴露电镀金属层; 并且将金属层和电镀金属层中的至少一个图案化为电路层。

公开(公告)号：US07875809B2

公开(公告)日：2011-01-25

申请号：US11766194

申请日：2007-06-21

Applicant: Chien-Wei Chang ,  Ting-Hao Lin ,  Jen-Fang Chang ,  Yu-Te Lu ,  Chia-Chi Lo

Inventor： Chien-Wei Chang ,  Ting-Hao Lin ,  Jen-Fang Chang ,  Yu-Te Lu ,  Chia-Chi Lo

IPC: H05K1/00

CPC classification number: H05K3/4602 ,  H05K3/108 ,  H05K3/427 ,  H05K2201/0347 ,  H05K2201/09536 ,  H05K2201/0959 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49165

Abstract: A circuit board includes a core layer substrate having a plated through hole filled with a dielectric material. The plated through hole has a sidewall coated with an inner electroless copper layer, and an electroplated metal layer plated on the inner electroless copper layer before the plated through hole is filled with the dielectric material. The outer portion of the filled plated through hole is thicker than the center portion and tapered toward the center portion to form a depressed surface on the filled plated through hole. The core layer substrate is covered with a patterned electroless copper layer and a patterned electroplated copper layer that connect with the inner electroless copper layer and electroplated metal layer of the plated through hole. The patterned electroplated copper layer forms a flat copper pad above the plated through hole.

Abstract translation: 电路板包括具有填充有介电材料的电镀通孔的芯层基板。 电镀通孔具有涂覆有内部化学镀铜层的侧壁和在电镀通孔填充有电介质材料之前镀在内部化学镀铜层上的电镀金属层。 填充电镀通孔的外部比中心部分厚，并且朝向中心部分逐渐变细，以在填充的电镀通孔上形成凹陷表面。 芯层衬底被覆有图案化的无电铜层和与电镀通孔的内部化学镀铜层和电镀金属层连接的图案化电镀铜层。 图案化的电镀铜层在电镀通孔上方形成平坦的铜焊盘。