公开(公告)号：US20210118799A1

公开(公告)日：2021-04-22

申请号：US16660448

申请日：2019-10-22

Applicant: Tokyo Electron Limited

Inventor： Lars Liebmann ,  Jeffrey Smith ,  Anton deVilliers

IPC: H01L23/528 ,  H01L27/092 ,  H01L25/07 ,  H01L21/768

Abstract: Aspects of the disclosure provide a semiconductor apparatus including a plurality of structures. A first one of the structures comprises a first stack of transistors that includes a first transistor formed on a substrate and a second transistor stacked on the first transistor along a Z direction substantially perpendicular to a substrate plane of the semiconductor apparatus. The first one of the structures further includes local interconnect structures. The first transistor is sandwiched between two of the local interconnect structures. The first one of the structures further includes vertical conductive structures substantially parallel to the Z direction. The vertical conductive structures are configured to provide at least power supplies for the first one of the structures by electrically coupling with the local interconnect structures. A height of one of the vertical conductive structures along the Z direction is at least a height of the first one of the structures.

公开(公告)号：US20190287795A1

公开(公告)日：2019-09-19

申请号：US16357946

申请日：2019-03-19

Applicant: Tokyo Electron Limited

Inventor： Anton deVilliers ,  Ronald Nasman ,  Jeffrey Smith

IPC: H01L21/027 ,  G03F7/20 ,  H01L21/02 ,  G03F7/00

Abstract: Techniques herein include processes and systems by which a reproducible CD variation pattern can be mitigated or corrected to yield desirable CDs from microfabrication patterning processes, via resolution enhancement. A repeatable portion of CD variation across a set of wafers is identified, and then a correction exposure pattern is generated. A direct-write projection system exposes this correction pattern on a substrate as a component exposure, augmentation exposure, or partial exposure. A conventional mask-based photolithographic system executes a primary patterning exposure as a second or main component exposure. The two component exposures when combined enhance resolution of the patterning exposure to improve CDs on the substrate being processed without measure each wafer.

公开(公告)号：US20180040695A1

公开(公告)日：2018-02-08

申请号：US15671771

申请日：2017-08-08

Applicant: TOKYO ELECTRON LIMITED

Inventor： Jeffrey Smith ,  Anton deVilliers ,  Nihar Mohanty ,  Subhadeep Kal ,  Kandabara Tapily

IPC: H01L29/06 ,  H01L27/11 ,  H01L21/8238 ,  H01L29/423

CPC classification number: H01L29/0676 ,  H01L21/823807 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/1104 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775

Abstract: A semiconductor device including a substrate and a gate region of a field effect transistor formed on the substrate. The gate region includes vertically stacked nanowires having longitudinal axes that extend parallel with a working surface of the substrate. A given stack of vertically stacked nanowires includes at least two nanowires vertically aligned in which a p-type nanowire and an n-type nanowire are spatially separated from each other vertically. The semiconductor device further Includes a step-shaped connecting structure formed within the gate region that electrically connects each nanowire to positions above the gate region. A first gate electrode has a step-shaped profile and connects to a first-level nanowire.

公开(公告)号：US09718082B2

公开(公告)日：2017-08-01

申请号：US14600821

申请日：2015-01-20

Applicant: Tokyo Electron Limited

Inventor： Anton deVilliers ,  Ronald Nasman ,  James Grootegoed ,  Norman A. Jacobson, Jr.

IPC: B05C5/02 ,  B05C11/10 ,  B05C9/10 ,  H01L21/67

CPC classification number: B05C5/0225 ,  B05C5/0204 ,  B05C9/10 ,  B05C11/1013 ,  H01L21/67017 ,  H01L21/67051 ,  Y10T137/7787

Abstract: A fluid dispensing apparatus is disclosed. Systems include an in-line or linear bladder apparatus configured to expand to collect a charge of fluid, and contract to assist with fluid delivery and dispensing. During a dispense-off period process fluid can collect in this bladder after the process fluid is pushed through a fine filter (micro filter). A given filtration rate can be less than a dispense rate and thus the system herein compensates for filter-lag that often accompanies fluid filtering for microfabrication, while providing a generally linear configuration that reduces chances for defect creation.

公开(公告)号：US20250068823A1

公开(公告)日：2025-02-27

申请号：US18615365

申请日：2024-03-25

Applicant: Tokyo Electron Limited

Inventor： Henry Jim Fulford ,  Partha Mukhopadhyay ,  Zuriel CARIBE ,  Anton deVilliers

IPC: G06F30/398 ,  G06F30/392 ,  G06F113/18 ,  G06F119/02 ,  G06F119/08 ,  H01L23/00

Abstract: A method includes receiving a first layout file for a first workpiece and a second layout file for a second workpiece. First layout file and second layout file are analyzed to identify contact points, which are grouped into bins. A contact point of a first bin is simulated using a simulation model. Contact point includes a first feature of the first workpiece and a second feature of the second workpiece. In response to determining that the contact point does not have desired properties, a first layout of the first feature and a second layout of the second feature are updated to determine an updated contact point. Updated contact point is simulated using the simulation model. In response to determining that the updated contact point has the desired properties, first layout file is updated to include updated first layout, and second layout file is updated to include updated second layout.

公开(公告)号：US11574845B2

公开(公告)日：2023-02-07

申请号：US16848638

申请日：2020-04-14

Applicant: TOKYO ELECTRON LIMITED

Inventor： Daniel Chanemougame ,  Lars Liebmann ,  Jeffrey Smith ,  Anton deVilliers

IPC: H01L21/8238 ,  H01L27/092

Abstract: A method of manufacturing a 3D semiconductor device, the method including forming a first target structure, the first target structure including at least one upper gate, at least one bottom gate, and a dielectric separation layer disposed between and separating the at least one upper gate and the at least one bottom gate; removing material in a plurality of material removal areas in the first target structure, the plurality of material removal areas including at least one material removal area that extends through the at least one upper gate to a top of the dielectric separation layer; and forming a first contact establishing a first electrical connection to the upper gate and a second contact establishing a second electrical connection to the at least one bottom gate, such that the first contact and second contact are independent of each other.

公开(公告)号：US20230024975A1

公开(公告)日：2023-01-26

申请号：US17954953

申请日：2022-09-28

Applicant: Tokyo Electron Limited

Inventor： Lars Liebmann ,  Jeffrey Smith ,  Anton deVilliers

IPC: H01L23/528 ,  H01L27/092 ,  H01L21/768 ,  H01L25/07

Abstract: A method for forming a semiconductor apparatus includes forming a plurality of repetitive initial structures over a substrate of the semiconductor apparatus. An initial structure in the plurality of repetitive initial structures is formed by forming a first stack of transistors along a Z direction substantially perpendicular to a substrate plane, and forming local interconnect structures. Each of the transistors in the first stack of transistors is sandwiched between two of the local interconnect structures. Vertical conductive structures are formed substantially parallel to the Z direction, a height of one of the vertical conductive structures along the Z direction being at least a height of the initial structure. The initial structure is functionalized into a final structure by forming one or more connections each electrically coupling one of the local interconnect structures to one of the vertical conductive structures.

公开(公告)号：US11488947B2

公开(公告)日：2022-11-01

申请号：US16847001

申请日：2020-04-13

Applicant: Tokyo Electron Limited

Inventor： Lars Liebmann ,  Jeffrey Smith ,  Daniel Chanemougame ,  Anton deVilliers

IPC: H01L27/02 ,  H01L27/06

Abstract: An integrated circuit includes an array of unit cells, each unit cell of which including field effect transistors arranged in a stack. Local interconnect structures form select conductive paths between select terminals of the field effect transistors to define cell circuitry that is confined within each unit cell. An array of contacts is disposed on an accessible surface of the unit cell, where each contact is electrically coupled to a corresponding electrical node of the cell circuitry.

公开(公告)号：US11443953B2

公开(公告)日：2022-09-13

申请号：US16682607

申请日：2019-11-13

Applicant: Tokyo Electron Limited

Inventor： Kandabara N. Tapily ,  Anton deVilliers ,  Gerrit J. Leusink

IPC: H01L21/31 ,  H01L21/469 ,  H01L21/311 ,  H01L21/02

Abstract: A processing method includes receiving a substrate containing a base layer having a mandrel pattern formed thereon containing a number of features, conformally depositing a silicon oxide film over the mandrel pattern by coating surfaces of the substrate with a metal-containing catalyst layer, and in the absence of any oxidizing and hydrolyzing agent, exposing the substrate to a process gas containing a silanol gas at a substrate temperature selected to yield a preferred level of stress in the silicon oxide film. The method further includes removing the silicon oxide film from upper surfaces of the mandrel pattern and lower surfaces adjacent the mandrel pattern to leave behind silicon oxide sidewall spacers on sidewalls of the mandrel pattern, and removing the mandrel pattern from the substrate to leave behind the silicon oxide sidewall spacers that form a new pattern having double the number of features of the removed mandrel pattern.

公开(公告)号：US10916637B2

公开(公告)日：2021-02-09

申请号：US16435411

申请日：2019-06-07

Applicant: TOKYO ELECTRON LIMITED

Inventor： Jeffrey Smith ,  Anton deVilliers

IPC: H01L29/00 ,  H01L29/66 ,  H01L29/775 ,  B82Y10/00 ,  H01L29/40 ,  H01L29/786 ,  H01L29/08 ,  H01L21/02 ,  H01L21/28 ,  H01L29/06 ,  H01L29/423

Abstract: A method of forming a gate-all-around semiconductor device, includes providing a substrate having a layered fin structure thereon. The layered fin structure includes a channel portion and a sacrificial portion each extending along a length of the layered fin structure, wherein the layered fin structure being covered with replacement gate material. A dummy gate is formed on the replacement gate material over the layered fin structure, wherein the dummy gate having a critical dimension which extends along the length of the layered fin structure. The method further includes forming a gate structure directly under the dummy gate, the gate structure including a metal gate region and gate spacers provided on opposing sides of the metal gate region, wherein a total critical dimension of the gate structure is equal to the critical dimension of the dummy gate.