公开(公告)号：US09799550B2

公开(公告)日：2017-10-24

申请号：US14845294

申请日：2015-09-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Hao Huang ,  Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  Chieh-Te Chen ,  Shang-Yuan Tsai

IPC: H01L21/02 ,  H01L21/441 ,  H01L21/768 ,  H01L21/311 ,  H01L21/033 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L21/76802 ,  H01L21/0332 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32134 ,  H01L21/76877 ,  H01L21/76897 ,  H01L29/41791 ,  H01L2029/7858

Abstract: The present invention provides a method for forming an opening, including: first, a hard mask material layer is formed on a target layer, next, a tri-layer hard mask is formed on the hard mask material layer, where the tri-layer hard mask includes an bottom organic layer (ODL), a middle silicon-containing hard mask bottom anti-reflection coating (SHB) layer and a top photoresist layer, and an etching process is then performed, to remove parts of the tri-layer hard mask, parts of the hard mask material layer and parts of the target layer in sequence, so as to form at least one opening in the target layer, where during the step for removing parts of the hard mask material layer, a lateral etching rate of the hard mask material layer is smaller than a lateral etching rate of the ODL.

公开(公告)号：US09728455B2

公开(公告)日：2017-08-08

申请号：US15404163

申请日：2017-01-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  Chieh-Te Chen

IPC: H01L21/20 ,  H01L21/768 ,  H01L23/535 ,  H01L23/532

CPC classification number: H01L21/76895 ,  H01L21/76805 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/53295 ,  H01L23/535 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a gate structure thereon and an interlayer dielectric (ILD) layer surrounding the gate structure; forming a sacrificial layer on the gate structure; forming a first contact plug in the sacrificial layer and the ILD layer; removing the sacrificial layer; and forming a first dielectric layer on the gate structure and the first contact plug.

公开(公告)号：US09543203B1

公开(公告)日：2017-01-10

申请号：US14791242

申请日：2015-07-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  En-Chiuan Liou ,  Chia-Hsun Tseng ,  Wei-Hao Huang ,  Yu-Ting Hung

IPC: H01L21/3205 ,  H01L29/66 ,  H01L21/768 ,  H01L21/311 ,  H01L21/027

CPC classification number: H01L21/76897 ,  H01L21/0276 ,  H01L21/31133 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76877 ,  H01L29/66545 ,  H01L29/6656

Abstract: A method of fabricating a semiconductor structure includes the following steps: forming a first interlayer dielectric on a substrate; forming a gate electrode on the substrate so that the periphery of the gate electrode is surrounded by the first interlayer dielectric; forming a patterned mask layer comprising at least a layer of organic material on the gate electrode; forming a conformal dielectric layer to conformally cover the layer of organic material; and forming a second interlayer dielectric to cover the conformal dielectric layer.

Abstract translation: 制造半导体结构的方法包括以下步骤：在衬底上形成第一层间电介质; 在所述基板上形成栅电极，使得所述栅电极的周围被所述第一层间电介质包围; 在所述栅电极上形成至少包含一层有机材料的图案化掩模层; 形成保形绝缘层以保形地覆盖有机材料层; 以及形成覆盖所述共形介电层的第二层间电介质。

公开(公告)号：US20170004997A1

公开(公告)日：2017-01-05

申请号：US14791242

申请日：2015-07-02

Applicant: United Microelectronics Corp.

Inventor： Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  En-Chiuan Liou ,  Chia-Hsun Tseng ,  Wei-Hao Huang ,  Yu-Ting Hung

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/027 ,  H01L29/66

CPC classification number: H01L21/76897 ,  H01L21/0276 ,  H01L21/31133 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76877 ,  H01L29/66545 ,  H01L29/6656

Abstract: A method of fabricating a semiconductor structure includes the following steps: forming a first interlayer dielectric on a substrate; forming a gate electrode on the substrate so that the periphery of the gate electrode is surrounded by the first interlayer dielectric; forming a patterned mask layer comprising at least a layer of organic material on the gate electrode; forming a conformal dielectric layer to conformally cover the layer of organic material; and forming a second interlayer dielectric to cover the conformal dielectric layer.

Abstract translation: 制造半导体结构的方法包括以下步骤：在衬底上形成第一层间电介质; 在所述基板上形成栅电极，使得所述栅电极的周围被所述第一层间电介质包围; 在所述栅电极上形成至少包含一层有机材料的图案化掩模层; 形成保形绝缘层以保形地覆盖有机材料层; 以及形成覆盖所述共形介电层的第二层间电介质。

公开(公告)号：US09530851B1

公开(公告)日：2016-12-27

申请号：US14841661

申请日：2015-08-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Lin Lu ,  Chun-Lung Chen ,  En-Chiuan Liou ,  Chih-Wei Yang ,  Yu-Cheng Tung ,  Kun-Yuan Liao ,  Feng-Yi Chang

IPC: H01L29/78 ,  H01L21/8238 ,  H01L29/423 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L29/42364 ,  H01L21/823468 ,  H01L21/823475 ,  H01L27/088 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7843

Abstract: The present invention provides a semiconductor device, including at least two gate structures, and each gate structure includes a gate, a spacer and a source/drain region, the source/drain region disposed on two sides of the gate. A first dielectric layer is disposed on the substrate and between two gate structures, where the first dielectric layer has a concave surface, and the first dielectric layer directly contacts the spacer. A floating spacer is disposed on the first dielectric layer and on a sidewall of the gate, and at least one contact plug is disposed on the source/drain region, where the contact plug directly contacts the floating spacer.

Abstract translation: 本发明提供一种包括至少两个栅极结构的半导体器件，并且每个栅极结构包括栅极，间隔物和源极/漏极区域，源极/漏极区域设置在栅极的两侧。 第一电介质层设置在衬底上并且在两个栅极结构之间，其中第一电介质层具有凹面，并且第一电介质层直接接触间隔物。 浮动间隔物设置在第一介电层上和栅极的侧壁上，并且至少一个接触插塞设置在源极/漏极区上，其中接触插塞直接接触浮动间隔物。

公开(公告)号：US20160064528A1

公开(公告)日：2016-03-03

申请号：US14509070

申请日：2014-10-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L29/66545 ,  H01L29/785

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a metal gate thereon and a hard mask atop the metal gate; and performing a high-density plasma (HDP) process to form a cap layer on the hard mask and the substrate.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有金属栅极的基板和在金属栅极顶部的硬掩模; 以及执行高密度等离子体（HDP）工艺以在硬掩模和基板上形成盖层。

公开(公告)号：US09263294B2

公开(公告)日：2016-02-16

申请号：US14273283

申请日：2014-05-08

Applicant: United Microelectronics Corp.

Inventor： Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  Chieh-Te Chen ,  Cheng-Hsing Chuang

IPC: H01L21/4763 ,  H01L21/311

CPC classification number: H01L21/31111 ,  H01L21/31133 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76897

Abstract: A method of forming a semiconductor device is provided. A material layer, a first flowing material layer and a first mask layer are sequentially formed on a substrate. A first etching process is performed by using the first mask layer as a mask, so as to form a first opening in the material layer. The first mask layer and the first flowing material layer are removed. A filler layer is formed in the first opening. A second flowing material layer is formed on the material layer and the filler layer. A second mask layer is formed on the second flowing material layer. A second etching process is performed by using the second mask layer as a mask, so as to form a second opening in the material layer.

Abstract translation: 提供一种形成半导体器件的方法。 在基板上依次形成材料层，第一流动材料层和第一掩模层。 通过使用第一掩模层作为掩模来进行第一蚀刻工艺，以在材料层中形成第一开口。 去除第一掩模层和第一流动材料层。 在第一开口中形成填充层。 在材料层和填料层上形成第二流动材料层。 在第二流动材料层上形成第二掩模层。 通过使用第二掩模层作为掩模来进行第二蚀刻处理，以在材料层中形成第二开口。

公开(公告)号：US20160027892A1

公开(公告)日：2016-01-28

申请号：US14852624

申请日：2015-09-13

Applicant: United Microelectronics Corp.

Inventor： Ching-Ling Lin ,  Chih-Sen Huang ,  Shih-Fang Tzou ,  Chien-Ting Lin ,  Yi-Wei Chen ,  Shi-Xiong Lin ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  Hsiao-Pang Chou ,  Chia-Lin Lu

IPC: H01L29/49 ,  H01L29/423 ,  H01L27/088

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/823456 ,  H01L21/82385 ,  H01L27/088 ,  H01L29/4232 ,  H01L29/517 ,  H01L29/66545

Abstract: The metal gate structure includes at least a substrate, a dielectric layer, first and second trenches, first metal layer and second metal layers, and two cap layers. In particular, the dielectric layer is disposed on the substrate, and the first and second trenches are disposed in the dielectric layer. The width of the first trench is less than the width of the second trench. The first and second metal layers are respectively disposed in the first trench and the second trench, and the height of the first metal layer is less than or equal to the height of the second metal layer. The cap layers are respectively disposed in a top surface of the first metal layer and a top surface of the second metal layer.

Abstract translation: 金属栅极结构至少包括衬底，电介质层，第一和第二沟槽，第一金属层和第二金属层以及两个盖层。 特别地，介电层设置在基板上，并且第一和第二沟槽设置在电介质层中。 第一沟槽的宽度小于第二沟槽的宽度。 第一和第二金属层分别设置在第一沟槽和第二沟槽中，第一金属层的高度小于或等于第二金属层的高度。 盖层分别设置在第一金属层的顶表面和第二金属层的顶表面中。

公开(公告)号：US09214392B1

公开(公告)日：2015-12-15

申请号：US14527778

申请日：2014-10-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/768 ,  H01L23/535 ,  H01L23/532 ,  H01L21/311

CPC classification number: H01L21/823475 ,  H01L21/76832 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823437 ,  H01L23/485 ,  H01L27/0886 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a contact hole includes providing a substrate. A nitrogen-containing dielectric layer, a first material layer, a second material layer, an oxygen-containing dielectric layer and a patterned photoresist layer cover the substrate from bottom to top. Then, the oxygen-containing dielectric layer is etched by taking the second material layer as a first etching stop layer to form a patterned oxygen-containing dielectric layer. Latter, the second material layer is etched by taking the first material layer as a second etching stop layer to form a patterned second material layer. Subsequently, the first material layer is etched by taking the nitrogen-containing dielectric layer as a third etching stop layer to form a patterned first material layer. Finally, the nitrogen-containing dielectric layer is etched until the substrate is exposed.

Abstract translation: 形成接触孔的方法包括提供基板。 含氮介电层，第一材料层，第二材料层，含氧介电层和图案化的光致抗蚀剂层从底部到顶部覆盖基板。 然后，通过将第二材料层作为第一蚀刻停止层来蚀刻含氧电介质层，以形成图案化的含氧电介质层。 通过将第一材料层作为第二蚀刻停止层来蚀刻第二材料层以形成图案化的第二材料层。 随后，通过将含氮介电层作为第三蚀刻停止层来蚀刻第一材料层，以形成图案化的第一材料层。 最后，对含氮介电层进行蚀刻，直到基片露出。

公开(公告)号：US09209273B1

公开(公告)日：2015-12-08

申请号：US14463677

申请日：2014-08-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Ling Lin ,  Chih-Sen Huang ,  Shih-Fang Tzou ,  Chien-Ting Lin ,  Yi-Wei Chen ,  Shi-Xiong Lin ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  Hsiao-Pang Chou ,  Chia-Lin Lu

IPC: H01L21/4763 ,  H01L29/66 ,  H01L27/088 ,  H01L29/51 ,  H01L29/49 ,  H01L21/3213 ,  H01L21/8234 ,  H01L21/8238

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/823456 ,  H01L21/82385 ,  H01L27/088 ,  H01L29/4232 ,  H01L29/517 ,  H01L29/66545

Abstract: A method for fabricating a metal gate structure includes providing a substrate on which a dielectric layer, a first trench disposed in the dielectric layer, a first metal layer filling up the first trench, a second trench disposed in the dielectric layer, a second metal layer filling up the second trench are disposed, and the width of the first trench is less than the width of the second trench; forming a mask layer to completely cover the second trench; performing a first etching process to remove portions of the first metal layer when the second trench is covered by the mask layer; and performing a second etching process to concurrently remove portions of the first metal layer and portions of the second metal layer after the first etching process.

Abstract translation: 一种用于制造金属栅极结构的方法，包括：提供基板，其上布置介电层，设置在电介质层中的第一沟槽，填充第一沟槽的第一金属层，设置在电介质层中的第二沟槽，第二金属层 设置填充第二沟槽，并且第一沟槽的宽度小于第二沟槽的宽度; 形成掩模层以完全覆盖所述第二沟槽; 当所述第二沟槽被所述掩模层覆盖时，执行第一蚀刻工艺以去除所述第一金属层的部分; 以及执行第二蚀刻工艺，以在第一蚀刻工艺之后同时去除第一金属层的部分和第二金属层的部分。