公开(公告)号：US09898569B2

公开(公告)日：2018-02-20

申请号：US14852635

申请日：2015-09-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hsien Wu ,  Chen-Hsien Hsu ,  Wei-Jen Wang ,  Chien-Fu Chen ,  Chien-Hung Chen

IPC: H01L21/70 ,  G06F17/50 ,  H01L27/02

CPC classification number: G06F17/5072 ,  H01L21/823437 ,  H01L27/0207 ,  H01L27/088

Abstract: A method for designing a semiconductor layout structure includes following steps. A first active feature group including at least a first active feature is received, and the first active feature includes a first channel length. A pair of first dummy features is introduced to form a first cell pattern. The first dummy features include a first dummy width. A first spacing width is defined between the first active feature group and one of the first dummy features and a third spacing width is defined between the first active feature group and the other first dummy feature. The first cell pattern includes a first cell width and a first poly pitch, and the first cell width is a multiple of the first pitch. The receiving of the first active feature group and the introducing of the first dummy features are performed in by at least a computer-aided design tool.

公开(公告)号：US09837493B2

公开(公告)日：2017-12-05

申请号：US14940867

申请日：2015-11-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Hung Chen ,  Shih-Hsien Huang ,  Yu-Ru Yang ,  Huai-Tzu Chiang ,  Hao-Ming Lee ,  Sheng-Hao Lin ,  Cheng-Tzung Tsai ,  Chun-Yuan Wu

IPC: H01L29/165 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3065 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/165 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/30604 ,  H01L21/3065 ,  H01L29/0657 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device comprises a semiconductor substrate and a semiconductor fin. The semiconductor substrate has an upper surface and a recess extending downwards into the semiconductor substrate from the upper surface. The semiconductor fin is disposed in the recess and extends upwards beyond the upper surface, wherein the semiconductor fin is directly in contact with semiconductor substrate, so as to form at least one semiconductor hetero-interface on a sidewall of the recess.

公开(公告)号：US20170117414A1

公开(公告)日：2017-04-27

申请号：US14941674

申请日：2015-11-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Hsien Huang ,  Chien-Hung Chen ,  Chun-Yuan Wu ,  Kun-Hsin Chen ,  Tien-I Wu ,  Yu-Ru Yang ,  Huai-Tzu Chiang

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/06 ,  H01L21/324 ,  H01L29/66 ,  H01L29/167 ,  H01L29/10

CPC classification number: H01L29/66795 ,  H01L21/324 ,  H01L21/823412 ,  H01L21/823431 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/167 ,  H01L29/785 ,  H01L29/7851 ,  H01L2029/7858 ,  H01L2924/13067

Abstract: A semiconductor structure including a semiconductor substrate and at least a fin structure formed thereon. The semiconductor substrate includes a first semiconductor material. The fin structure includes a first epitaxial layer and a second epitaxial layer formed between the first epitaxial layer and the semiconductor substrate. The first epitaxial layer includes the first semiconductor material and a second semiconductor material. A lattice constant of the second semiconductor material is different from a lattice constant of the first semiconductor material. The second epitaxial layer includes the first semiconductor material and the second semiconductor material. The second epitaxial layer further includes conductive dopants.

公开(公告)号：US09349815B2

公开(公告)日：2016-05-24

申请号：US14488295

申请日：2014-09-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuan-Yi Tseng ,  Tzu-Ping Chen ,  Chun-Lung Chang ,  Chih-Haw Lee ,  Wei-Shiang Huang ,  Chien-Hung Chen

IPC: H01L21/336 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/42368 ,  H01L21/28035 ,  H01L21/28158 ,  H01L29/66575 ,  H01L29/6659 ,  H01L29/78 ,  H01L29/7833

Abstract: A gate structure is provided. The gate structure includes a substrate, a gate disposed on the substrate and a gate dielectric layer disposed between the substrate and the gate, wherein the gate dielectric layer is in the shape of a barbell. The barbell has a thin center connecting to two bulging ends. Part of the bulging ends extends into the gate and the substrate.

Abstract translation: 提供了栅极结构。 栅极结构包括衬底，设置在衬底上的栅极和设置在衬底和栅极之间的栅极电介质层，其中栅极电介质层为杠铃形状。 杠铃具有连接到两个凸起端的薄中心。 凸出部分的一部分延伸到栅极和衬底中。

公开(公告)号：US20150356231A1

公开(公告)日：2015-12-10

申请号：US14337187

申请日：2014-07-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chao-Yao Chiang ,  Kuo-Hsun Huang ,  Chien-Hung Chen

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5068

Abstract: A planar design to non-planar design conversion method includes following steps. At least a diffusion region pattern including a first side and a second side perpendicular to each other is received. A look-up table is queried to obtain a first positive integer according to the first side of the diffusion region pattern and a second positive integer according to the second side of the diffusion region pattern. Then, a plurality of fin patterns is formed. An amount of the fin patterns is equal to the second positive integer. The fin patterns respectively include a first fin length, and the first fin length is a product of the first positive integer and a predetermined value. The forming is performed by at least a computer-aided design (CAD) tool.

Abstract translation: 非平面设计转换方法的平面设计包括以下步骤。 至少包括彼此垂直的第一侧和第二侧的扩散区图案。 查询表根据扩散区域图案的第一侧获得第一正整数，并根据扩散区图案的第二侧获得第二正整数。 然后，形成多个翅片图案。 鳍图案的数量等于第二正整数。 翅片图案分别包括第一翅片长度，并且第一翅片长度是第一正整数和预定值的乘积。 至少由计算机辅助设计（CAD）工具进行成型。

公开(公告)号：US08837220B2

公开(公告)日：2014-09-16

申请号：US13741442

申请日：2013-01-15

Applicant: United Microelectronics Corp.

Inventor： Shen-De Wang ,  Wen-Chung Chang ,  Ya-Huei Huang ,  Feng-Ji Tsai ,  Chien-Hung Chen

IPC: G11C11/34 ,  G11C16/14 ,  H01L27/088 ,  G11C16/10

CPC classification number: G11C16/14 ,  G11C16/0475 ,  G11C16/10 ,  H01L21/28282 ,  H01L27/088 ,  H01L27/11565 ,  H01L27/11568

Abstract: A manipulating method of a nonvolatile memory is provided and comprises following steps. The nonvolatile memory having a plurality of memory cell is provided. Two adjacent memory cells correspond to one bit and comprise a substrate, a first and another first doping regions, a second doping region, a charge trapping layer, a control gate, a first bit line, a source line and a second bit line different from the first bit line. A first and a second channel are formed. The charge trapping layer is disposed on the first and the second channels. The two adjacent memory cells are programmed by following steps. A first positive and negative voltages are applied to the control gate between the first and the second doping regions and the control gate between the second and the another first doping regions, respectively. A first voltage is applied to the source line.

Abstract translation: 提供了一种非易失性存储器的操作方法，包括以下步骤。 提供具有多个存储单元的非易失性存储器。 两个相邻的存储器单元对应于一个位，并且包括基板，第一和第二第一掺杂区域，第二掺杂区域，电荷俘获层，控制栅极，第一位线，源极线和与 第一个位线。 形成第一和第二通道。 电荷捕获层设置在第一和第二通道上。 通过以下步骤对相邻的两个存储单元进行编程。 第一正电压和负电压分别施加到第一和第二掺杂区域之间的控制栅极以及第二和第二掺杂区域之间的控制栅极。 第一个电压被施加到源极线。

公开(公告)号：US20140197472A1

公开(公告)日：2014-07-17

申请号：US13741399

申请日：2013-01-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Chung Chang ,  Shen-De Wang ,  Ya-Huei Huang ,  Feng-Ji Tsai ,  Chien-Hung Chen

IPC: H01L29/66 ,  H01L29/792

CPC classification number: H01L29/66833 ,  H01L21/28282 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/4234 ,  H01L29/792

Abstract: A method for manufacturing a non-volatile memory structure includes providing a substrate having a memory region and a logic region defined thereon, masking the logic region while forming at least a first gate in the memory region, forming an oxide-nitride-oxide (ONO) structure under the first gate, forming an oxide structure covering the ONO structure on the substrate, masking the memory region while forming a second gate in the logic region, and forming a first spacer on sidewalls of the first gate and a second spacer on sidewalls of the second gate simultaneously.

Abstract translation: 一种用于制造非易失性存储器结构的方法包括提供具有存储区域和限定在其上的逻辑区域的衬底，在形成存储区域中的至少第一栅极的同时屏蔽逻辑区域，形成氧化物 - 氧化物 - 氧化物（ONO ）结构，在衬底上形成覆盖ONO结构的氧化物结构，在逻辑区域中形成第二栅极的同时掩蔽存储区域，以及在第一栅极的侧壁上形成第一间隔物，在侧壁上形成第二间隔物 的第二个门。

公开(公告)号：US20230097189A1

公开(公告)日：2023-03-30

申请号：US17868770

申请日：2022-07-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Hung Chen ,  Ruei-Yau Chen ,  Wei-Jen Wang ,  Kun-Yuan Wu ,  Chien-Fu Chen ,  Chen-Hsien Hsu

IPC: G06F30/392 ,  G06F30/30

Abstract: A method for forming an integrated circuit layout including at least two standard cells having different cell heights is disclosed. The standard cells respectively have a well boundary to divide a PMOS region and an NMOS region. The standard cells are abutted side by side along their side edges in a way that the well boundaries of the cells are aligned along the row direction. The power rail and the ground rail of one of the standard cells are shifted to align and connect to the power rail and the ground rail of the other one of the standard cells.

公开(公告)号：US11461693B2

公开(公告)日：2022-10-04

申请号：US16105182

申请日：2018-08-20

Applicant: United Microelectronics Corp.

Inventor： Yao-Sheng Chang ,  Ya-Ching Cheng ,  Chien-Hung Chen ,  Chih-Yueh Li ,  Da-Ching Liao

IPC: G06N20/00 ,  G06F17/16 ,  G06F5/01

Abstract: A training apparatus and a training method for providing a sample size expanding model are provided. A normalizing unit receives a training data set with at least one numeric predictor factor and a numeric response factor. An encoding unit trains the training data set in an initial encoding layer and at least one deep encoding layer. A modeling unit extracts a mean vector and a variance vector and inputting the mean vector and the variance vector together into a latent hidden layer for obtaining the sample size expanding model. A decoding unit trains the training data set in at least one deep decoding layer and a last encoding layer. A verifying unit performs a verification of the sample size expanding model according to the outputting data set. A data generating unit generates a plurality of samples via the sample size expanding model.

公开(公告)号：US11074376B2

公开(公告)日：2021-07-27

申请号：US15497489

申请日：2017-04-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ya-Ching Cheng ,  Chun-Liang Hou ,  Chien-Hung Chen ,  Wen-Jung Liao ,  Min-Chin Hsieh ,  Da-Ching Liao ,  Li-Chin Wang

IPC: G06F30/20

Abstract: A method for analyzing a process output and a method for creating an equipment parameter model are provided. The method for analyzing the process output includes the following steps: A plurality of process steps are obtained. A processor obtains a step model set including a plurality of first step regression models, each of which represents a relationship between N of the process steps and a process output. The processor calculates a correlation of each of the first step regression models. The processor picks up at least two of the first step regression models to be a plurality of second step regression models whose correlations are ranked at top among the correlations of the first step regression models. The processor updates the step model set by a plurality of third step regression models, each of which represents a relationship between M of the process steps and the process output.