公开(公告)号：US20240136423A1

公开(公告)日：2024-04-25

申请号：US18395657

申请日：2023-12-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Ming Chang ,  Che-Hung Huang ,  Wen-Jung Liao ,  Chun-Liang Hou

IPC: H01L29/66 ,  H01L29/778

CPC classification number: H01L29/66462 ,  H01L29/7786

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a first barrier layer on the buffer layer; forming a first hard mask on the first barrier layer; removing the first hard mask and the first barrier layer to form a recess; forming a second barrier layer in the recess; and forming a p-type semiconductor layer on the second barrier layer.

公开(公告)号：US20240038847A1

公开(公告)日：2024-02-01

申请号：US17892098

申请日：2022-08-21

Applicant: United Microelectronics Corp.

Inventor： Chih Tung Yeh ,  Chun-Liang Hou

IPC: H01L29/20 ,  H01L29/66 ,  H01L29/778 ,  H01L21/285

CPC classification number: H01L29/2003 ,  H01L29/66462 ,  H01L29/7786 ,  H01L21/28587

Abstract: A gallium nitride device and a method for manufacturing a high electron mobility transistor are provided. The gallium nitride device includes a substrate, a channel layer disposed on the substrate, a barrier layer disposed on the channel layer, a cap layer disposed on the barrier layer, a gate disposed on the cap layer, a source, a drain, and ohmic sidewall dams. The source and the drain are formed in the cap layer and the barrier layer. Each of the source and the drain has a trench portion, and a contact below the trench portion and protruding into the channel layer. The ohmic sidewall dams are disposed on a sidewall of the trench portion of each of the source and the drain.

公开(公告)号：US11074376B2

公开(公告)日：2021-07-27

申请号：US15497489

申请日：2017-04-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ya-Ching Cheng ,  Chun-Liang Hou ,  Chien-Hung Chen ,  Wen-Jung Liao ,  Min-Chin Hsieh ,  Da-Ching Liao ,  Li-Chin Wang

IPC: G06F30/20

Abstract: A method for analyzing a process output and a method for creating an equipment parameter model are provided. The method for analyzing the process output includes the following steps: A plurality of process steps are obtained. A processor obtains a step model set including a plurality of first step regression models, each of which represents a relationship between N of the process steps and a process output. The processor calculates a correlation of each of the first step regression models. The processor picks up at least two of the first step regression models to be a plurality of second step regression models whose correlations are ranked at top among the correlations of the first step regression models. The processor updates the step model set by a plurality of third step regression models, each of which represents a relationship between M of the process steps and the process output.

公开(公告)号：US20210036138A1

公开(公告)日：2021-02-04

申请号：US16558329

申请日：2019-09-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Ming Chang ,  Chun-Liang Hou ,  Wen-Jung Liao

IPC: H01L29/778 ,  H01L29/20 ,  H01L21/306 ,  H01L29/66

Abstract: A high electron mobility transistor (HEMT) includes a substrate; a buffer layer over the substrate, a GaN layer over the buffer layer, a first AlGaN layer over the GaN layer, a first AlN layer over the AlGaN layer, and a p-GaN layer over the first AlN layer.

公开(公告)号：US10861970B1

公开(公告)日：2020-12-08

申请号：US16596773

申请日：2019-10-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Ming Chang ,  Chun-Liang Hou ,  Wen-Jung Liao ,  Ming-Chang Lu

IPC: H01L29/20 ,  H01L29/78 ,  H01L29/66 ,  H01L29/778

Abstract: A semiconductor epitaxial structure with reduced defects, including a substrate with a recess formed thereon, an island insulator on a bottom surface of the recess, spacers on sidewalls of the recess, a buffer layer in the recess and covering the island insulator, a channel layer in the recess and on the buffer layer, and a barrier layer in the recess and on the channel layer, wherein two-dimensional electron gas (2DEG) or two-dimensional hole gas (2DHG) is formed in the channel layer.

公开(公告)号：US20190266214A1

公开(公告)日：2019-08-29

申请号：US15905263

申请日：2018-02-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Ching LIAO ,  Li-Chin Wang ,  Ya-Ching Cheng ,  Chien-Hung Chen ,  Chun-Liang Hou

IPC: G06F17/15

Abstract: An analyzing method and an analyzing system for manufacturing data are provided. The analyzing method includes the following steps. A plurality of models each of which has a correlation value representing a relationship between at least one of a plurality of factors and a target parameter are provided. The models are screened according to the correlation values. A rank information and a frequency information of the factors are listed up according to the models. The factors are screened according to the rank information and the frequency information. The models are ranked and at least one of the models is selected.

公开(公告)号：US09171127B1

公开(公告)日：2015-10-27

申请号：US14509074

申请日：2014-10-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Liang Hou ,  Wen-Jung Liao ,  Chi-Fang Huang ,  Yi-Jung Chang

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G03F7/70433

Abstract: A design layout generating method is provided. A design layout including a first pattern and a second pattern is provided to a computer system, wherein the first pattern and the second pattern meet a design rule of an integrated circuit, respectively. The first pattern and the second pattern are combined into a third pattern. Next, the third pattern is checked if it meets a definition of a weak pattern, wherein the weak pattern is a pattern that meets the design rule but still forms defects. Then, the third pattern is modified and a new design layout is generated.

Abstract translation: 提供了一种设计布局生成方法。 将包括第一图案和第二图案的设计布局提供给计算机系统，其中第一图案和第二图案分别满足集成电路的设计规则。 第一图案和第二图案被组合成第三图案。 接下来，如果它符合弱图案的定义，则检查第三图案，其中弱图案是符合设计规则但仍形成缺陷的图案。 然后，修改第三个模式并生成新的设计布局。

公开(公告)号：US12266701B2

公开(公告)日：2025-04-01

申请号：US18199359

申请日：2023-05-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Tung Yeh ,  Chun-Liang Hou ,  Wen-Jung Liao ,  Chun-Ming Chang ,  Yi-Shan Hsu ,  Ruey-Chyr Lee

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L29/66 ,  H01L29/778

Abstract: A high electron mobility transistor includes a substrate, a mesa structure disposed on the substrate, a passivation layer disposed on the mesa structure, and at least a contact structure disposed in the passivation layer and the mesa structure. The mesa structure includes a channel layer, a barrier layer on the channel layer, two opposite first edges extending along a first direction, and two opposite second edges extending along a second direction. The contact structure includes a body portion and a plurality of protruding portions. The body portion penetrates through the passivation layer. The protruding portions penetrate through the barrier layer and a portion of the channel layer. In a top view, the body portion overlaps the two opposite first edges of the mesa structure without overlapping the two opposite second edges of the mesa structure.

公开(公告)号：US20240014310A1

公开(公告)日：2024-01-11

申请号：US18371440

申请日：2023-09-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shin-Chuan Huang ,  Chih-Tung Yeh ,  Chun-Ming Chang ,  Bo-Rong Chen ,  Wen-Jung Liao ,  Chun-Liang Hou

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/778

CPC classification number: H01L29/66462 ,  H01L29/2003 ,  H01L29/7786

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; forming a hard mask on the barrier layer; performing an implantation process through the hard mask to form a doped region in the barrier layer and the buffer layer; removing the hard mask and the barrier layer to form a first trench; forming a gate dielectric layer on the hard mask and into the first trench; forming a gate electrode on the gate dielectric layer; and forming a source electrode and a drain electrode adjacent to two sides of the gate electrode.

公开(公告)号：US20230378314A1

公开(公告)日：2023-11-23

申请号：US18221404

申请日：2023-07-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Bo-Rong Chen ,  Che-Hung Huang ,  Chun-Ming Chang ,  Yi-Shan Hsu ,  Chih-Tung Yeh ,  Shin-Chuan Huang ,  Wen-Jung Liao ,  Chun-Liang Hou

IPC: H01L29/66 ,  H01L29/778 ,  H01L29/20

CPC classification number: H01L29/66462 ,  H01L29/7783 ,  H01L29/2003

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a first barrier layer on a substrate; forming a p-type semiconductor layer on the first barrier layer; forming a hard mask on the p-type semiconductor layer; patterning the hard mask and the p-type semiconductor layer; and forming a spacer adjacent to the hard mask and the p-type semiconductor layer.