公开(公告)号：US20170104070A1

公开(公告)日：2017-04-13

申请号：US14940867

申请日：2015-11-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Hung Chen ,  Shih-Hsien Huang ,  Yu-Ru Yang ,  Huai-Tzu Chiang ,  Hao-Ming Lee ,  Sheng-Hao Lin ,  Cheng-Tzung Tsai ,  Chun-Yuan Wu

IPC: H01L29/165 ,  H01L21/306 ,  H01L21/3065 ,  H01L29/06 ,  H01L21/02

CPC classification number: H01L29/165 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/30604 ,  H01L21/3065 ,  H01L29/0657 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device comprises a semiconductor substrate and a semiconductor fin. The semiconductor substrate has an upper surface and a recess extending downwards into the semiconductor substrate from the upper surface. The semiconductor fin is disposed in the recess and extends upwards beyond the upper surface, wherein the semiconductor fin is directly in contact with semiconductor substrate, so as to form at least one semiconductor hetero-interface on a sidewall of the recess.

公开(公告)号：US20170092771A1

公开(公告)日：2017-03-30

申请号：US14953036

申请日：2015-11-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Fu Hsu ,  Chun-Yuan Wu ,  Xu Yang Shen ,  ZHIBIAO ZHOU ,  Qinggang Xing

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/78696

Abstract: A semiconductor device and a method of fabricating the same, the semiconductor device includes a substrate, an interconnect structure, and an oxide semiconductor structure. The substrate has a first region and a second region. The interconnect structure is disposed on the substrate, in the first region. The oxide semiconductor structure is disposed over a hydrogen blocking layer, in the second region of the substrate.

公开(公告)号：US09431441B1

公开(公告)日：2016-08-30

申请号：US14834452

申请日：2015-08-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhibiao Zhou ,  Shao-Hui Wu ,  Chi-Fa Ku ,  Chen-Bin Lin ,  Chun-Yuan Wu ,  Chia-Fu Hsu

IPC: H01L29/10 ,  H01L27/146 ,  H01L29/786

CPC classification number: H01L27/14612 ,  H01L27/1225 ,  H01L27/1255 ,  H01L27/1463 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14643 ,  H01L29/7869

Abstract: A back side illumination image sensor pixel structure includes a substrate having a front side and a back side opposite to the front side, a sensing device formed in the substrate to receive an incident light through the back side of the substrate, two oxide-semiconductor field effect transistor (OS FET) devices formed on the front side of the substrate, and a capacitor formed on the front side of the substrate. The two OS FET devices are directly stacked on the sensing device and the capacitor is directly stacked on the OS FET devices. The two OS FET devices overlap the sensing device, and the capacitor overlaps both of the OS FET devices and the sensing device.

Abstract translation: 背面照明图像传感器像素结构包括具有与前侧相反的前侧和后侧的基板，形成在基板中以接收穿过基板的背面的入射光的感测装置，两个氧化物半导体场 形成在基板的前侧的效应晶体管（OS FET）器件，以及形成在基板的前侧的电容器。 两个OS FET器件直接堆叠在感测器件上，电容器直接堆叠在OS FET器件上。 两个OS FET器件与感测器件重叠，并且电容器与OS FET器件和感测器件重叠。

公开(公告)号：US09412590B1

公开(公告)日：2016-08-09

申请号：US14840055

申请日：2015-08-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Fu Hsu ,  Chun-Yuan Wu

IPC: H01L21/321 ,  H01L21/4763 ,  H01L21/02 ,  H01L29/66 ,  H01L21/28 ,  H01L21/283

CPC classification number: H01L29/66477 ,  H01L21/02323 ,  H01L21/02554 ,  H01L21/02658 ,  H01L27/1207 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: A manufacturing method of an oxide semiconductor device includes the following steps. A barrier layer is formed on a substrate. An annealing process is performed after the step of forming the barrier layer. A first oxygen treatment is performed on the barrier layer after the annealing process for forming a first oxygen provider layer on the barrier layer. An oxide semiconductor layer is then formed on the first oxygen provider layer.

Abstract translation: 氧化物半导体器件的制造方法包括以下步骤。 在基板上形成阻挡层。 在形成阻挡层的步骤之后进行退火处理。 在阻挡层上形成第一氧供体层的退火处理之后，在阻挡层上进行第一次氧处理。 然后在第一氧供体层上形成氧化物半导体层。

公开(公告)号：US09349873B1

公开(公告)日：2016-05-24

申请号：US14825511

申请日：2015-08-13

Applicant: United Microelectronics Corp.

Inventor： Zhi-Biao Zhou ,  Shao-Hui Wu ,  Chi-Fa Ku ,  Chen-Bin Lin ,  Chun-Yuan Wu

IPC: H01L21/441 ,  H01L29/786 ,  H01L29/66 ,  H01L29/417 ,  H01L29/423 ,  H01L21/768 ,  H01L29/24

CPC classification number: H01L29/7869 ,  H01L27/1218 ,  H01L27/124 ,  H01L27/1248 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/66969 ,  H01L29/78603 ,  H01L29/78606 ,  H01L29/78648

Abstract: Provided is an oxide semiconductor device. A source, a drain, and a first gate are buried in a first dielectric layer, and the first gate is located between the source and the drain. A first barrier layer is located on the first dielectric layer, partially overlaps the source and the drain and overlaps the first gate. The first barrier layer includes a first opening and a second opening respectively corresponds to the source and the drain. An oxide semiconductor layer covers the first barrier layer and fills in the first opening and the second opening. A second barrier layer is located on the oxide semiconductor layer. A second gate is located on the second barrier layer and overlaps with the source, the drain, and the first gate.

Abstract translation: 提供一种氧化物半导体器件。 源极，漏极和第一栅极被埋在第一电介质层中，并且第一栅极位于源极和漏极之间。 第一阻挡层位于第一电介质层上，部分地与源极和漏极重叠并与第一栅极重叠。 第一阻挡层包括第一开口和第二开口，分别对应于源极和漏极。 氧化物半导体层覆盖第一阻挡层并填充在第一开口和第二开口中。 第二阻挡层位于氧化物半导体层上。 第二栅极位于第二阻挡层上并与源极，漏极和第一栅极重叠。

公开(公告)号：US20160071800A1

公开(公告)日：2016-03-10

申请号：US14513230

申请日：2014-10-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Tsung-Hung Chang ,  Yi-Hui Lee ,  Chih-Sen Huang ,  Yi-Wei Chen ,  Chia Chang Hsu ,  Hsin-Fu Huang ,  Chun-Yuan Wu ,  Shih-Fang Tzou

IPC: H01L23/535 ,  H01L21/768

CPC classification number: H01L21/76879 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76855 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure including a dielectric layer, a titanium layer, a titanium nitride layer and a metal is provided. The dielectric layer is disposed on a substrate, wherein the dielectric layer has a via. The titanium layer covers the via, wherein the titanium layer has tensile stress lower than 1500 Mpa. The titanium nitride layer conformally covers the titanium layer. The metal fills the via. The present invention also provides a semiconductor process for forming said semiconductor structure. The semiconductor process includes the following steps. A dielectric layer is formed on a substrate, wherein the dielectric has a via. A titanium layer conformally covers the via, wherein the titanium layer has compressive stress lower than 500 Mpa. A titanium nitride layer is formed to conformally cover the titanium layer. A metal fills the via.

Abstract translation: 提供了包括电介质层，钛层，氮化钛层和金属的半导体结构。 电介质层设置在基板上，其中介电层具有通孔。 钛层覆盖通孔，其中钛层具有低于1500Mpa的拉伸应力。 氮化钛层共形地覆盖钛层。 金属填充通孔。 本发明还提供了一种用于形成所述半导体结构的半导体工艺。 半导体工艺包括以下步骤。 介电层形成在基板上，其中电介质具有通孔。 钛层保形地覆盖通孔，其中钛层具有低于500Mpa的压应力。 形成氮化钛层以保形地覆盖钛层。 金属填充通孔。

公开(公告)号：US20150303283A1

公开(公告)日：2015-10-22

申请号：US14279340

申请日：2014-05-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chin-Cheng Chien ,  Chun-Yuan Wu ,  Ted Ming-Lang Guo

IPC: H01L29/66

CPC classification number: H01L29/66803 ,  H01L29/7848

Abstract: A method for manufacturing a semiconductor device includes the following steps. A substrate including at least a fin layer and a plurality of gate electrodes is provided. A tilt and twist ion implantation is performed to form a plurality of doped regions in the fin layer. An etching process is performed to remove the doped regions to form a plurality of recesses in the fin layer.

Abstract translation: 一种制造半导体器件的方法包括以下步骤。 提供至少包括翅片层和多个栅电极的基板。 进行倾斜和扭转离子注入以在翅片层中形成多个掺杂区域。 执行蚀刻处理以去除掺杂区域以在散热片层中形成多个凹部。

公开(公告)号：US08779513B2

公开(公告)日：2014-07-15

申请号：US13869037

申请日：2013-04-24

Applicant: United Microelectronics Corp.

Inventor： Shih-Hung Tsai ,  Chien-Ting Lin ,  Chin-Cheng Chien ,  Chin-Fu Lin ,  Chih-Chien Liu ,  Teng-Chun Tsai ,  Chun-Yuan Wu

IPC: H01L27/12 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/66795

Abstract: A non-planar semiconductor structure includes a substrate, at least two fin-shaped structures, at least an isolation structure, and a plurality of epitaxial layers. The fin-shaped structures are located on the substrate. The isolation structure is located between the fin-shaped structures, and the isolation structure has a nitrogen-containing layer. The epitaxial layers respectively cover a part of the fin-shaped structures and are located on the nitrogen-containing layer. A non-planar semiconductor process is also provided for forming the semiconductor structure.

Abstract translation: 非平面半导体结构包括衬底，至少两个鳍状结构，至少一个隔离结构和多个外延层。 鳍状结构位于基底上。 隔离结构位于鳍状结构之间，隔离结构具有含氮层。 外延层分别覆盖了鳍状结构的一部分并且位于含氮层上。 还提供了用于形成半导体结构的非平面半导体工艺。

公开(公告)号：US11476367B2

公开(公告)日：2022-10-18

申请号：US17409461

申请日：2021-08-23

Applicant: United Microelectronics Corp.

Inventor： Yen-Chen Chen ,  Xiao Wu ,  Hai Tao Liu ,  Ming Hua Du ,  Shouguo Zhang ,  Yao-Hung Liu ,  Chin-Fu Lin ,  Chun-Yuan Wu

IPC: H01L29/786 ,  H01L29/24 ,  H01L29/66 ,  H01L29/45 ,  H01L29/417

Abstract: A semiconductor device includes an oxide semiconductor layer, disposed over a substrate. A source electrode of a metal nitride is disposed on the oxide semiconductor layer. A drain electrode of the metal nitride is disposed on the oxide semiconductor layer. A metal-nitride oxidation layer is formed on a surface of the source electrode and the drain electrode. A ratio of a thickness of the metal-nitride oxidation layer to a thickness of the drain electrode or the source electrode is equal to or less than 0.2.

公开(公告)号：US20210384359A1

公开(公告)日：2021-12-09

申请号：US17409461

申请日：2021-08-23

Applicant: United Microelectronics Corp.

Inventor： Yen-Chen Chen ,  Xiao Wu ,  Hai Tao Liu ,  Ming Hua Du ,  Shouguo Zhang ,  Yao-Hung Liu ,  Chin-Fu Lin ,  Chun-Yuan Wu

IPC: H01L29/786 ,  H01L29/24 ,  H01L29/66 ,  H01L29/45 ,  H01L29/417

Abstract: A semiconductor device includes an oxide semiconductor layer, disposed over a substrate. A source electrode of a metal nitride is disposed on the oxide semiconductor layer. A drain electrode of the metal nitride is disposed on the oxide semiconductor layer. A metal-nitride oxidation layer is formed on a surface of the source electrode and the drain electrode. A ratio of a thickness of the metal-nitride oxidation layer to a thickness of the drain electrode or the source electrode is equal to or less than 0.2.