公开(公告)号：US09502410B1

公开(公告)日：2016-11-22

申请号：US14792591

申请日：2015-07-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Wei Feng ,  Shih-Hung Tsai ,  Hon-Huei Liu ,  Chao-Hung Lin ,  Nan-Yuan Huang ,  Jyh-Shyang Jenq

IPC: H01L27/088 ,  H01L29/78 ,  H01L21/28 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/306 ,  H01L27/092

CPC classification number: H01L21/823431 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/823481 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/42372 ,  H01L29/7842 ,  H01L29/785

Abstract: The present invention provides a semiconductor structure, including a substrate having a first fin structure and a second fin structure disposed thereon, a first isolation region located between the first fin structure and the second fin structure, a second isolation region located opposite the first fin structure from the first isolation region, and at least an epitaxial layer disposed on the side of the first fin structure and the second fin structure. The epitaxial layer has a bottom surface, the bottom surface extending from the first fin structure to the second fin structure, and the bottom surface is lower than a bottom surface of the first isolation region and a top surface of the second isolation region.

Abstract translation: 本发明提供了一种半导体结构，其包括具有第一鳍结构和设置在其上的第二鳍结构的衬底，位于第一鳍结构和第二鳍结构之间的第一隔离区，与第一鳍结构相对的第二隔离区 并且至少设置在第一鳍片结构和第二鳍片结构侧的外延层。 外延层具有从第一鳍结构延伸到第二鳍结构的底表面，底表面低于第一隔离区的底表面和第二隔离区的顶表面。

公开(公告)号：US20160233088A1

公开(公告)日：2016-08-11

申请号：US14637400

申请日：2015-03-04

Applicant: United Microelectronics Corp.

Inventor： Li-Wei Feng ,  Shih-Hung Tsai ,  Chao-Hung Lin ,  Hon-Huei Liu ,  Shih-Fang Hong ,  Jyh-Shyang Jenq

IPC: H01L21/225 ,  H01L27/092 ,  H01L21/033 ,  H01L21/8238 ,  H01L21/324

CPC classification number: H01L21/823821 ,  H01L21/2255 ,  H01L21/2256 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823892 ,  H01L27/0924 ,  H01L29/66803 ,  H01L29/7851

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having at least one fin-shaped structure thereon, in which the fin-shaped structure comprises a top portion and a bottom portion; and forming a doped layer and a first liner around the bottom portion of the fin-shaped structure.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有至少一个鳍状结构的基底，其中鳍状结构包括顶部和底部; 以及围绕所述鳍状结构的底部部分形成掺杂层和第一衬垫。

公开(公告)号：US20160204197A1

公开(公告)日：2016-07-14

申请号：US14612300

申请日：2015-02-03

Applicant: United Microelectronics Corp.

Inventor： En-Chiuan Liou ,  Ssu-I Fu ,  Chia-Lin Lu ,  Shih-Hung Tsai ,  Chih-Wei Yang ,  Chia-Ching Lin ,  Chia-Hsun Tseng ,  Rai-Min Huang

IPC: H01L29/06 ,  H01L21/762

CPC classification number: H01L29/0684 ,  H01L21/76 ,  H01L21/762 ,  H01L21/76232 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/6681 ,  H01L29/7846 ,  H01L29/7851

Abstract: The present invention provides a semiconductor structure, including a substrate, a shallow trench isolation (STI) disposed in the substrate, a plurality of first fin structures disposed in the substrate, where each first fin structure and the substrate have same material, and a plurality of second fin structures disposed in the STI, where each second fin structure and the STI have same material.

Abstract translation: 本发明提供一种半导体结构，包括基板，设置在基板中的浅沟槽隔离（STI），设置在基板中的多个第一翅片结构，其中每个第一翅片结构和基板具有相同的材料，以及多个 设置在STI中的第二鳍结构，其中每个第二鳍结构和STI具有相同的材料。

公开(公告)号：US09349833B1

公开(公告)日：2016-05-24

申请号：US14614416

申请日：2015-02-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Hsiang Hung ,  Chao-Hung Lin ,  Ying-Tsung Chen ,  Chih-Kai Hsu ,  Ssu-I Fu ,  Jyh-Shyang Jenq ,  Shih-Hung Tsai

IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/311 ,  H01L21/28 ,  H01L27/088 ,  H01L23/535

CPC classification number: H01L29/6656 ,  H01L21/823468 ,  H01L21/823475 ,  H01L23/485 ,  H01L27/088 ,  H01L29/4983 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a plurality of gate structures, a source/drain region, a first dielectric layer, and a floating spacer. The gate structures are disposed on a substrate, and each gate structure includes a gate electrode, a capping layer and a spacer surrounding the gate electrode and the capping layer. The source/drain region is disposed at two sides of the gate electrode. The first dielectric layer is disposed on the substrate and has a height being less than a height of the gate electrode. The floating spacer is disposed on a side wall of the spacer, and also on the first dielectric layer.

Abstract translation: 半导体器件包括多个栅极结构，源极/漏极区，第一电介质层和浮置间隔物。 栅极结构设置在衬底上，并且每个栅极结构包括栅电极，覆盖层和围绕栅电极和覆盖层的间隔物。 源极/漏极区域设置在栅电极的两侧。 第一介电层设置在基板上，其高度小于栅电极的高度。 浮动间隔件设置在间隔件的侧壁上，也位于第一介电层上。

公开(公告)号：US09268896B1

公开(公告)日：2016-02-23

申请号：US14576212

申请日：2014-12-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Hsien Tang ,  Shih-Hung Tsai ,  Chun-Hsien Huang ,  Yao-Jen Fan

IPC: G06F17/50

CPC classification number: G03F1/38 ,  G03F1/70 ,  G03F7/70425 ,  H01L21/823431

Abstract: A method of forming a photomask comprises providing a predetermined fin array having a plurality of fin patterns to a computer readable medium in a computer system. First of all, a plurality of width markers is defined by using the computer system, with each of the width marker parallel to each other and comprising two fin patterns, wherein each of the width markers is spaced from each other by a space. Then, a number of the width markers is checked to be an even. Following this, a plurality of pre-mandrel patterns is defined corresponding to odd numbered ones of the spaces. Then, a plurality of mandrel patterns is defined by sizing up the pre-mandrel patterns. Finally, the mandrel patterns are outputted to form a photomask.

Abstract translation: 形成光掩模的方法包括向计算机系统中的计算机可读介质提供具有多个鳍图案的预定鳍阵列。 首先，通过使用计算机系统来定义多个宽度标记，其中每个宽度标记彼此平行并且包括两个鳍图案，其中每个宽度标记彼此间隔一个空间。 然后，多个宽度标记被检查为均匀。 此后，对应于空格中的奇数编号的多个预心轴图案被定义。 然后，通过调整预心轴图案的尺寸来定义多个心轴图案。 最后，输出心轴图案以形成光掩模。

公开(公告)号：US09105685B2

公开(公告)日：2015-08-11

申请号：US13941208

申请日：2013-07-12

Applicant: United Microelectronics Corp.

Inventor： Chien-Ting Lin ,  Shih-Hung Tsai ,  Chun-Hsien Lin

IPC: H01L21/762 ,  H01L21/308 ,  H01L21/8238 ,  H01L21/84 ,  H01L21/8234

CPC classification number: H01L21/76224 ,  H01L21/308 ,  H01L21/3086 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/845

Abstract: A method of forming a shallow trench isolation structure is disclosed. Hard mask patterns are formed on a substrate. A portion of the substrate is removed, using the hard mask patterns as a mask, to form first trenches in the substrate, wherein a fin is disposed between the neighboring first trenches. A filling layer is formed in the first trenches. A patterned mask layer is formed on the filling layer. A portion of the filling layer and a portion of the fins are removed, using the patterned mask layer as a mask, to form second trenches in the substrate. A first insulating layer is formed on the substrate filling in the second trenches.

Abstract translation: 公开了形成浅沟槽隔离结构的方法。 在基板上形成硬掩模图案。 使用硬掩模图案作为掩模去除衬底的一部分，以在衬底中形成第一沟槽，其中翅片设置在相邻的第一沟槽之间。 在第一沟槽中形成填充层。 在填充层上形成图案化掩模层。 使用图案化掩模层作为掩模，去除填充层的一部分和散热片的一部分，以在衬底中形成第二沟槽。 在填充在第二沟槽中的衬底上形成第一绝缘层。

公开(公告)号：US09024393B2

公开(公告)日：2015-05-05

申请号：US14140546

申请日：2013-12-26

Applicant: United Microelectronics Corp.

Inventor： Ssu-I Fu ,  Wen-Tai Chiang ,  Ying-Tsung Chen ,  Shih-Hung Tsai ,  Chien-Ting Lin ,  Chi-Mao Hsu ,  Chin-Fu Lin

IPC: H01L21/02 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/66 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L21/28114 ,  H01L21/28088 ,  H01L21/823828 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

Abstract: A manufacturing method for semiconductor device having metal gate includes providing a substrate having a first semiconductor device and a second semiconductor device formed thereon, the first semiconductor device having a first gate trench and the second semiconductor device having a second gate trench; sequentially forming a high dielectric constant (high-k) gate dielectric layer and a multiple metal layer on the substrate; forming a first work function metal layer in the first gate trench; performing a first pull back step to remove a portion of the first work function metal layer from the first gate trench; forming a second work function metal layer in the first gate trench and the second gate trench; and performing a second pull back step to remove a portion of the second work function metal layer from the first gate trench and the second gate trench.

Abstract translation: 具有金属栅极的半导体器件的制造方法包括提供具有第一半导体器件和形成在其上的第二半导体器件的衬底，所述第一半导体器件具有第一栅极沟槽，所述第二半导体器件具有第二栅极沟槽; 在基板上依次形成高介电常数（高k）栅介质层和多金属层; 在所述第一栅极沟槽中形成第一功函数金属层; 执行第一拉回步骤以从所述第一栅极沟槽去除所述第一功函数金属层的一部分; 在所述第一栅极沟槽和所述第二栅极沟槽中形成第二功函数金属层; 以及执行第二拉回步骤以从所述第一栅极沟槽和所述第二栅极沟槽去除所述第二功函数金属层的一部分。

公开(公告)号：US20150004766A1

公开(公告)日：2015-01-01

申请号：US14487103

申请日：2014-09-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Hung Tsai ,  Ssu-I Fu ,  Ying-Tsung Chen ,  Chih-Wei Chen ,  Ying-Chih Lin ,  Chien-Ting Lin ,  Hsuan-Hsu Chen

IPC: H01L29/66 ,  H01L29/51

CPC classification number: H01L29/66795 ,  H01L29/51 ,  H01L29/66818 ,  H01L29/785

Abstract: The present invention provides a non-planar FET which includes a substrate, a fin structure, a sub spacer, a gate, a dielectric layer and a source/drain region. The fin structure is disposed on the substrate. The sub spacer is disposed only on a middle sidewall of the fin structure. The gate is disposed on the fin structure. The dielectric layer is disposed between the fin structure and the gate. The source/drain region is disposed in the fin structure. The present invention further provides a method of forming the same.

Abstract translation: 本发明提供一种非平面FET，其包括基板，鳍结构，子间隔物，栅极，电介质层和源极/漏极区域。 翅片结构设置在基板上。 子间隔件仅设置在翅片结构的中间侧壁上。 门设置在翅片结构上。 介电层设置在翅片结构和栅极之间。 源/漏区设置在鳍结构中。 本发明还提供一种形成该方法的方法。

公开(公告)号：US20140106557A1

公开(公告)日：2014-04-17

申请号：US14140546

申请日：2013-12-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ssu-I Fu ,  Wen-Tai Chiang ,  Ying-Tsung Chen ,  Shih-Hung Tsai ,  Chien-Ting Lin ,  Chi-Mao Hsu ,  Chin-Fu Lin

IPC: H01L21/28 ,  H01L21/8238

CPC classification number: H01L21/28114 ,  H01L21/28088 ,  H01L21/823828 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

Abstract: A manufacturing method for semiconductor device having metal gate includes providing a substrate having a first semiconductor device and a second semiconductor device formed thereon, the first semiconductor device having a first gate trench and the second semiconductor device having a second gate trench; sequentially forming a high dielectric constant (high-k) gate dielectric layer and a multiple metal layer on the substrate; forming a first work function metal layer in the first gate trench; performing a first pull back step to remove a portion of the first work function metal layer from the first gate trench; forming a second work function metal layer in the first gate trench and the second gate trench; and performing a second pull back step to remove a portion of the second work function metal layer from the first gate trench and the second gate trench.

Abstract translation: 具有金属栅极的半导体器件的制造方法包括提供具有第一半导体器件和形成在其上的第二半导体器件的衬底，所述第一半导体器件具有第一栅极沟槽，所述第二半导体器件具有第二栅极沟槽; 在基板上依次形成高介电常数（高k）栅介质层和多金属层; 在所述第一栅极沟槽中形成第一功函数金属层; 执行第一拉回步骤以从所述第一栅极沟槽去除所述第一功函数金属层的一部分; 在所述第一栅极沟槽和所述第二栅极沟槽中形成第二功函数金属层; 以及执行第二拉回步骤以从所述第一栅极沟槽和所述第二栅极沟槽去除所述第二功函数金属层的一部分。

公开(公告)号：US12027600B2

公开(公告)日：2024-07-02

申请号：US18201769

申请日：2023-05-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Kuang Hsieh ,  Shih-Hung Tsai ,  Ching-Wen Hung ,  Chun-Hsien Lin

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/16 ,  H01L29/45 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/1606 ,  H01L29/45 ,  H01L29/66045 ,  H01L29/78696

Abstract: A method for fabricating a nanowire transistor includes the steps of first forming a nanowire channel structure on a substrate, in which the nanowire channel structure includes first semiconductor layers and second semiconductor layers alternately disposed over one another. Next, a gate structure is formed on the nanowire channel structure and then a source/drain structure is formed adjacent to the gate structure, in which the source/drain structure is made of graphene.