公开(公告)号：US20150137196A1

公开(公告)日：2015-05-21

申请号：US14592872

申请日：2015-01-08

Applicant: United Microelectronics Corp.

Inventor： Wen-Tai Chiang ,  Chun-Hsien Lin

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L21/28518 ,  H01L21/28008 ,  H01L21/76804 ,  H01L21/76814 ,  H01L29/41725 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/516 ,  H01L29/517 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/785

Abstract: The present invention provides a MOS transistor, including a substrate, a gate oxide, a gate, a source/drain region and a silicide layer. The gate oxide is disposed on the substrate and the gate is disposed on the gate oxide. The source/drain region is disposed in the substrate at two sides of the gate. The silicide layer is disposed on the source/drain region, wherein the silicide layer includes a curved bottom surface and a curved top surface, both the curved top surface and the curved bottom surface bend toward the substrate and the curved top surface is sunken from two sides thereof, two ends of the silicide layer point tips raised up over the source/drain region and the silicide layer in the middle is thicker than the silicide layer in the peripheral, thereby forming a crescent structure. The present invention further provides a manufacturing method of the MOS transistor.

Abstract translation: 本发明提供一种MOS晶体管，其包括衬底，栅极氧化物，栅极，源极/漏极区域和硅化物层。 栅极氧化物设置在衬底上，并且栅极设置在栅极氧化物上。 源极/漏极区域设置在栅极两侧的衬底中。 硅化物层设置在源极/漏极区域上，其中硅化物层包括弯曲的底部表面和弯曲的顶部表面，弯曲的顶部表面和弯曲的底部表面都朝向衬底弯曲，并且弯曲的顶部表面从两个凹陷 侧面，硅化物层尖端的两端在源极/漏极区域上升起，中间的硅化物层比外围的硅化物层厚，从而形成新月形结构。 本发明还提供一种MOS晶体管的制造方法。

公开(公告)号：US09006091B2

公开(公告)日：2015-04-14

申请号：US14302047

申请日：2014-06-11

Applicant: United Microelectronics Corp.

Inventor： Shih-Hung Tsai ,  Ssu-I Fu ,  Ying-Tsung Chen ,  Chih-Wei Chen ,  Chien-Ting Lin ,  Wen-Tai Chiang

IPC: H01L21/338 ,  H01L29/66 ,  H01L21/283 ,  H01L21/28 ,  H01L21/762 ,  H01L29/78 ,  H01L29/51

CPC classification number: H01L29/6681 ,  H01L21/28088 ,  H01L21/28114 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/283 ,  H01L21/76224 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/785

Abstract: A method of forming a semiconductor device is provided. A first interfacial material layer is formed by a deposition process on a substrate. A dummy gate material layer is formed on the first interfacial material layer. The dummy gate material layer and the first interfacial material layer are patterned to form a stacked structure. An interlayer dielectric (ILD) layer is formed to cover the stacked structure. A portion of the ILD layer is removed to expose a top of the stacked structure. The stacked structure is removed to form a trench in the ILD layer. A second interfacial layer and a first high-k layer are conformally formed at least on a surface of the trench. A composite metal layer is formed to at least fill up the trench.

Abstract translation: 提供一种形成半导体器件的方法。 通过在衬底上的沉积工艺形成第一界面材料层。 在第一界面材料层上形成虚拟栅极材料层。 将虚拟栅材料层和第一界面材料层图案化以形成堆叠结构。 形成层间电介质（ILD）层以覆盖层叠结构。 去除ILD层的一部分以露出堆叠结构的顶部。 去除层叠结构以在ILD层中形成沟槽。 至少在沟槽的表面上共形地形成第二界面层和第一高k层。 复合金属层形成为至少填充沟槽。

公开(公告)号：US09379026B2

公开(公告)日：2016-06-28

申请号：US14847015

申请日：2015-09-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Ting Lin ,  Wen-Tai Chiang

IPC: H01L27/088 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/8234 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823821 ,  H01L29/517 ,  H01L29/66545

Abstract: A fin-shaped field-effect transistor process includes the following steps. A substrate is provided. A first fin-shaped field-effect transistor and a second fin-shaped field-effect transistor are formed on the substrate, wherein the first fin-shaped field-effect transistor includes a first metal layer and the second fin-shaped field-effect transistor includes a second metal layer. A treatment process is performed on the first fin-shaped field-effect transistor to adjust the threshold voltage of the first fin-shaped field-effect transistor. A fin-shaped field-effect transistor formed by said process is also provided.

Abstract translation: 鳍状场效应晶体管工艺包括以下步骤。 提供基板。 第一鳍状场效应晶体管和第二鳍状场效应晶体管形成在基板上，其中第一鳍状场效应晶体管包括第一金属层和第二鳍状场效应晶体管 包括第二金属层。 对第一鳍状场效应晶体管进行处理处理，以调整第一鳍状场效应晶体管的阈值电压。 还提供了通过所述方法形成的鳍状场效应晶体管。

公开(公告)号：US20140295660A1

公开(公告)日：2014-10-02

申请号：US14302047

申请日：2014-06-11

Applicant: United Microelectronics Corp.

Inventor： Shih-Hung Tsai ,  Ssu-I Fu ,  Ying-Tsung Chen ,  Chih-Wei Chen ,  Chien-Ting Lin ,  Wen-Tai Chiang

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/762 ,  H01L21/28

CPC classification number: H01L29/6681 ,  H01L21/28088 ,  H01L21/28114 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/283 ,  H01L21/76224 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/785

Abstract: A method of forming a semiconductor device is provided. A first interfacial material layer is formed by a deposition process on a substrate. A dummy gate material layer is formed on the first interfacial material layer. The dummy gate material layer and the first interfacial material layer are patterned to form a stacked structure. An interlayer dielectric (ILD) layer is formed to cover the stacked structure. A portion of the ILD layer is removed to expose a top of the stacked structure. The stacked structure is removed to form a trench in the ILD layer. A second interfacial layer and a first high-k layer are conformally foamed at least on a surface of the trench. A composite metal layer is formed to at least fill up the trench.

Abstract translation: 提供一种形成半导体器件的方法。 通过在衬底上的沉积工艺形成第一界面材料层。 在第一界面材料层上形成虚拟栅极材料层。 将虚拟栅材料层和第一界面材料层图案化以形成堆叠结构。 形成层间电介质（ILD）层以覆盖层叠结构。 去除ILD层的一部分以露出堆叠结构的顶部。 去除层叠结构以在ILD层中形成沟槽。 第二界面层和第一高k层至少在沟槽的表面上保形发泡。 复合金属层形成为至少填充沟槽。

公开(公告)号：US20130252387A1

公开(公告)日：2013-09-26

申请号：US13895376

申请日：2013-05-16

Applicant: United Microelectronics Corp.

Inventor： Shih-Hung Tsai ,  Wen-Tai Chiang ,  Chen-Hua Tsai ,  Cheng-Tzung Tsai

IPC: H01L21/8234

CPC classification number: H01L21/823443 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823864 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7843

Abstract: A method for fabricating a metal-gate CMOS device. A substrate having thereon a first region and a second region is provided. A first dummy gate structure and a second dummy gate structure are formed within the first region and the second region respectively. A first LDD is formed on either side of the first dummy gate structure and a second LDD is formed on either side of the second dummy gate structure. A first spacer is formed on a sidewall of the first dummy gate structure and a second spacer is formed on a sidewall of the second dummy gate structure. A first embedded epitaxial layer is then formed in the substrate adjacent to the first dummy gate structure. The first region is masked with a seal layer. Thereafter, a second embedded epitaxial layer is formed in the substrate adjacent to the second dummy gate structure.

Abstract translation: 一种制造金属栅CMOS器件的方法。 提供其上具有第一区域和第二区域的基板。 第一虚拟栅极结构和第二虚拟栅极结构分别形成在第一区域和第二区域内。 第一LDD形成在第一虚拟栅极结构的两侧，第二LDD形成在第二虚拟栅极结构的任一侧上。 第一间隔物形成在第一伪栅极结构的侧壁上，第二间隔物形成在第二虚拟栅极结构的侧壁上。 然后在与第一伪栅极结构相邻的衬底中形成第一嵌入式外延层。 第一区域用密封层掩蔽。 此后，在与第二虚拟栅极结构相邻的衬底中形成第二嵌入式外延层。

公开(公告)号：US20160079071A1

公开(公告)日：2016-03-17

申请号：US14941648

申请日：2015-11-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Tai Chiang ,  Chun-Hsien Lin

IPC: H01L21/285 ,  H01L21/28

CPC classification number: H01L21/28518 ,  H01L21/28008 ,  H01L21/76804 ,  H01L21/76814 ,  H01L29/41725 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/516 ,  H01L29/517 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/785

Abstract: A manufacturing method of MOS transistor, the MOS transistor includes a substrate, a gate oxide, a gate, a source/drain region and a silicide layer. The gate oxide is disposed on the substrate and the gate is disposed on the gate oxide. The source/drain region is disposed in the substrate at two sides of the gate. The silicide layer is disposed on the source/drain region, wherein the silicide layer includes a curved bottom surface and a curved top surface, both the curved top surface and the curved bottom surface bend toward the substrate and the curved top surface is sunken from two sides thereof, two ends of the silicide layer point tips raised up over the source/drain region and the silicide layer in the middle is thicker than the silicide layer in the peripheral, thereby forming a crescent structure. The present invention further provides a manufacturing method of the MOS transistor.

Abstract translation: MOS晶体管的制造方法中，MOS晶体管包括基板，栅极氧化物，栅极，源极/漏极区域和硅化物层。 栅极氧化物设置在衬底上，并且栅极设置在栅极氧化物上。 源极/漏极区域设置在栅极两侧的衬底中。 硅化物层设置在源极/漏极区域上，其中硅化物层包括弯曲的底部表面和弯曲的顶部表面，弯曲的顶部表面和弯曲的底部表面都朝向衬底弯曲，并且弯曲的顶部表面从两个凹陷 侧面，硅化物层尖端的两端在源极/漏极区域上升起，中间的硅化物层比外围的硅化物层厚，从而形成新月形结构。 本发明还提供一种MOS晶体管的制造方法。

公开(公告)号：US20140077229A1

公开(公告)日：2014-03-20

申请号：US14089771

申请日：2013-11-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： An-Chi Liu ,  Chun-Hsien Lin ,  Yu-Cheng Tung ,  Chien-Ting Lin ,  Wen-Tai Chiang ,  Shih-Hung Tsai ,  Ssu-I Fu ,  Ying-Tsung Chen ,  Chih-Wei Chen

IPC: H01L29/78 ,  H01L29/786

CPC classification number: H01L29/7834 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78654

Abstract: A non-planar semiconductor structure comprises a substrate, at least one fin structure on the substrate, a gate covering parts of the fin structures and part of the substrate such that the fin structure is divided into a channel region stacking with the gate and source/drain region at both sides of the gate, a plurality of epitaxial structures covering on the source/drain region of the fin structures, a recess is provided between the channel region of the fin structure and the epitaxial structure, and a spacer formed on the sidewalls of the gate and the epitaxial structures, wherein the portion of the spacer filling in the recesses is flush with the top surface of the epitaxial structures.

Abstract translation: 非平面半导体结构包括衬底，衬底上的至少一个翅片结构，鳍覆盖部分的鳍结构和衬底的一部分，使得鳍结构被分成与栅极和源极/漏极堆叠的沟道区域， 漏极区域，覆盖在鳍状结构的源极/漏极区域上的多个外延结构，在鳍状结构的沟道区域和外延结构之间设置凹部，以及形成在侧壁上的间隔物 的栅极和外延结构，其中填充在凹槽中的间隔物的部分与外延结构的顶表面齐平。

公开(公告)号：US09875901B2

公开(公告)日：2018-01-23

申请号：US14941648

申请日：2015-11-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Tai Chiang ,  Chun-Hsien Lin

IPC: H01L29/76 ,  H01L21/285 ,  H01L29/417 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L21/768 ,  H01L21/28 ,  H01L29/78

CPC classification number: H01L21/28518 ,  H01L21/28008 ,  H01L21/76804 ,  H01L21/76814 ,  H01L29/41725 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/516 ,  H01L29/517 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/785

Abstract: A manufacturing method of MOS transistor, the MOS transistor includes a substrate, a gate oxide, a gate, a source/drain region and a silicide layer. The gate oxide is disposed on the substrate and the gate is disposed on the gate oxide. The source/drain region is disposed in the substrate at two sides of the gate. The silicide layer is disposed on the source/drain region, wherein the silicide layer includes a curved bottom surface and a curved top surface, both the curved top surface and the curved bottom surface bend toward the substrate and the curved top surface is sunken from two sides thereof, two ends of the silicide layer point tips raised up over the source/drain region and the silicide layer in the middle is thicker than the silicide layer in the peripheral, thereby forming a crescent structure. The present invention further provides a manufacturing method of the MOS transistor.

公开(公告)号：US20150380319A1

公开(公告)日：2015-12-31

申请号：US14847015

申请日：2015-09-08

Applicant: United Microelectronics Corp.

Inventor： Chien-Ting Lin ,  Wen-Tai Chiang

IPC: H01L21/8238 ,  H01L21/8234

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823821 ,  H01L29/517 ,  H01L29/66545

Abstract: A fin-shaped field-effect transistor process includes the following steps. A substrate is provided. A first fin-shaped field-effect transistor and a second fin-shaped field-effect transistor are formed on the substrate, wherein the first fin-shaped field-effect transistor includes a first metal layer and the second fin-shaped field-effect transistor includes a second metal layer. A treatment process is performed on the first fin-shaped field-effect transistor to adjust the threshold voltage of the first fin-shaped field-effect transistor. A fin-shaped field-effect transistor formed by said process is also provided.

Abstract translation: 鳍状场效应晶体管工艺包括以下步骤。 提供基板。 第一鳍状场效应晶体管和第二鳍状场效应晶体管形成在基板上，其中第一鳍状场效应晶体管包括第一金属层和第二鳍状场效应晶体管 包括第二金属层。 对第一鳍状场效应晶体管进行处理处理，以调整第一鳍状场效应晶体管的阈值电压。 还提供了通过所述方法形成的鳍状场效应晶体管。

公开(公告)号：US09219140B2

公开(公告)日：2015-12-22

申请号：US14592872

申请日：2015-01-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Tai Chiang ,  Chun-Hsien Lin

IPC: H01L29/76 ,  H01L29/78 ,  H01L21/285 ,  H01L29/417 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L21/768

CPC classification number: H01L21/28518 ,  H01L21/28008 ,  H01L21/76804 ,  H01L21/76814 ,  H01L29/41725 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/516 ,  H01L29/517 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/785

Abstract: The present invention provides a MOS transistor, including a substrate, a gate oxide, a gate, a source/drain region and a silicide layer. The gate oxide is disposed on the substrate and the gate is disposed on the gate oxide. The source/drain region is disposed in the substrate at two sides of the gate. The silicide layer is disposed on the source/drain region, wherein the silicide layer includes a curved bottom surface and a curved top surface, both the curved top surface and the curved bottom surface bend toward the substrate and the curved top surface is sunken from two sides thereof, two ends of the silicide layer point tips raised up over the source/drain region and the silicide layer in the middle is thicker than the silicide layer in the peripheral, thereby forming a crescent structure. The present invention further provides a manufacturing method of the MOS transistor.

Abstract translation: 本发明提供一种MOS晶体管，其包括衬底，栅极氧化物，栅极，源极/漏极区域和硅化物层。 栅极氧化物设置在衬底上，并且栅极设置在栅极氧化物上。 源极/漏极区域设置在栅极两侧的衬底中。 硅化物层设置在源极/漏极区域上，其中硅化物层包括弯曲的底部表面和弯曲的顶部表面，弯曲的顶部表面和弯曲的底部表面都朝向衬底弯曲，并且弯曲的顶部表面从两个凹陷 侧面，硅化物层尖端的两端在源极/漏极区域上升起，中间的硅化物层比外围的硅化物层厚，从而形成新月形结构。 本发明还提供一种MOS晶体管的制造方法。