公开(公告)号：US20170076995A1

公开(公告)日：2017-03-16

申请号：US14880693

申请日：2015-10-12

Applicant: United Microelectronics Corp.

Inventor： Yun-Tzu Chang ,  Shih-Min Chou ,  Kuo-Chih Lai ,  Ching-Yun Chang ,  Hsiang-Chieh Yen ,  Yen-Chen Chen ,  Yang-Ju Lu ,  Nien-Ting Ho ,  Chi-Mao Hsu

IPC: H01L21/8238

CPC classification number: H01L21/823842

Abstract: A method for modulating a work function of a semiconductor device having a metal gate structure including the following steps is provided. A first stacked gate structure and a second stacked gate structure having an identical structure are provided on a substrate. The first stacked gate structure and the second stacked gate structure respectively include a first work function metal layer of a first type. A patterned hard mask layer is formed. The patterned hard mask layer exposes the first work function metal layer of the first stacked gate structure and covers the first work function metal layer of the second stacked gate structure. A first gas treatment is performed to the first work function metal layer of the first stacked gate structure exposed by the patterned hard mask layer. A gas used in the first gas treatment includes nitrogen-containing gas or oxygen-containing gas.

Abstract translation: 提供了一种用于调制具有包括以下步骤的金属栅极结构的半导体器件的功函数的方法。 在基板上设置具有相同结构的第一堆叠栅极结构和第二堆叠栅极结构。 第一堆叠栅极结构和第二堆叠栅极结构分别包括第一类型的第一功函数金属层。 形成图案化的硬掩模层。 图案化的硬掩模层暴露第一堆叠栅极结构的第一功函数金属层并且覆盖第二堆叠栅极结构的第一功函数金属层。 对由图案化的硬掩模层暴露的第一堆叠栅极结构的第一功函数金属层进行第一气体处理。 在第一气体处理中使用的气体包括含氮气体或含氧气体。

公开(公告)号：US20160268259A1

公开(公告)日：2016-09-15

申请号：US14683128

申请日：2015-04-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Yun Chang ,  Chi-Mao Hsu ,  Wei-Ming Hsiao ,  Nien-Ting Ho ,  Kuo-Chih Lai

IPC: H01L27/092 ,  H01L21/8234 ,  H01L21/285 ,  H01L29/49 ,  H01L21/28

CPC classification number: H01L27/0922 ,  H01L21/28088 ,  H01L21/82345 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/4966 ,  H01L29/66545

Abstract: A semiconductor process of forming metal gates with different threshold voltages includes the following steps. A substrate having a first area and a second area is provided. A dielectric layer and a first work function layer are sequentially formed on the substrate of the first area and the second area. A second work function layer is directly formed on the first work function layer of the first area. A third work function layer is directly formed on the first work function layer of the second area, where the third work function layer is different from the second work function layer. The present invention also provides a semiconductor structure formed by said semiconductor process.

Abstract translation: 形成具有不同阈值电压的金属栅极的半导体工艺包括以下步骤。 提供具有第一区域和第二区域的衬底。 介电层和第一功函数层依次形成在第一区域和第二区域的基板上。 第二功能层直接形成在第一区域的第一功能层上。 第三功函数层直接形成在第二区域的第一功函数层上，其中第三功函数层与第二功函数层不同。 本发明还提供了由所述半导体工艺形成的半导体结构。

公开(公告)号：US09412653B2

公开(公告)日：2016-08-09

申请号：US14817227

申请日：2015-08-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jia-Jia Chen ,  Chi-Mao Hsu ,  Tsun-Min Cheng ,  Chun-Ling Lin ,  Huei-Ru Tsai ,  Ching-Wei Hsu ,  Chin-Fu Lin ,  Hsin-Yu Chen

IPC: H01L21/44 ,  H01L21/768

CPC classification number: H01L21/76847 ,  H01L21/76898 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A through silicon via structure is located in a recess of a substrate. The through silicon via structure includes a barrier layer, a buffer layer and a conductive layer. The barrier layer covers a surface of the recess. The buffer layer covers the barrier layer. The conductive layer is located on the buffer layer and fills the recess, wherein the contact surface between the conductive layer and the buffer layer is smoother than the contact surface between the buffer layer and the barrier layer. Moreover, a through silicon via process forming said through silicon via structure is also provided.

Abstract translation: 硅通孔结构位于衬底的凹槽中。 贯通硅通孔结构包括阻挡层，缓冲层和导电层。 阻挡层覆盖凹部的表面。 缓冲层覆盖阻挡层。 导电层位于缓冲层上并填充凹槽，其中导电层和缓冲层之间的接触表面比缓冲层和阻挡层之间的接触表面更平滑。 此外，还提供了形成所述贯穿硅通孔结构的通硅通孔工艺。

公开(公告)号：US20160104786A1

公开(公告)日：2016-04-14

申请号：US14543914

申请日：2014-11-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Yang ,  Yu-Feng Liu ,  Jian-Cun Ke ,  Chia-Fu Hsu ,  En-Chiuan Liou ,  Ssu-I Fu ,  Chi-Mao Hsu ,  Nien-Ting Ho ,  Yu-Ru Yang ,  Yu-Ping Wang ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Yu-Ting Tseng ,  Ya-Huei Tsai ,  Chien-Chung Huang ,  Tsung-Yin Hsieh ,  Hung-Yi Wu

IPC: H01L29/49 ,  H01L27/092 ,  H01L21/28 ,  H01L21/321 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/321 ,  H01L21/823431 ,  H01L21/82345 ,  H01L27/088 ,  H01L29/517 ,  H01L29/66545

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having an interlayer dielectric (ILD) layer thereon; forming a first recess, a second recess, and a third recess in the ILD layer; forming a material layer on the ILD layer and in the first recess, the second recess, and the third recess; performing a first treatment on the material layer in the first recess; and performing a second treatment on the material layer in the first recess and second recess.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有层间电介质（ILD）层的衬底; 在ILD层中形成第一凹槽，第二凹槽和第三凹槽; 在所述ILD层和所述第一凹部，所述第二凹部和所述第三凹部中形成材料层; 对所述第一凹部中的所述材料层进行第一处理; 以及对所述第一凹部和所述第二凹部中的所述材料层进行第二处理。

公开(公告)号：US09305847B2

公开(公告)日：2016-04-05

申请号：US14314425

申请日：2014-06-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shin-Chi Chen ,  Chih-Yueh Li ,  Shui-Yen Lu ,  Chi-Mao Hsu ,  Yuan-Chi Pai ,  Yu-Hong Kuo ,  Nien-Ting Ho

IPC: H01L21/8238 ,  H01L21/28 ,  H01L21/311 ,  H01L29/423

CPC classification number: H01L21/82385 ,  H01L21/28026 ,  H01L21/28088 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/823842 ,  H01L29/42376 ,  H01L29/66545

Abstract: A method of manufacturing a semiconductor device is provided. The method includes the following steps. A substrate including a first transistor having a first conductivity type, a second transistor having a second conductivity type and a third transistor having the first conductivity type is formed. An inner-layer dielectric layer is formed on the substrate, and includes a first gate trench corresponding to the first transistor, a second gate trench corresponding to the second transistor and a third gate trench corresponding to the third transistor. A work function metal layer is formed on the inner-layer dielectric layer. An anti-reflective layer is coated on the work function metal layer. The anti-reflective layer on the second transistor and on the top portion of the third gate trench is removed to expose the work function metal layer. The exposed work function metal layer is removed.

Abstract translation: 提供一种制造半导体器件的方法。 该方法包括以下步骤。 形成包括具有第一导电类型的第一晶体管，具有第二导电类型的第二晶体管和具有第一导电类型的第三晶体管的衬底。 内层电介质层形成在衬底上，并且包括对应于第一晶体管的第一栅极沟槽，对应于第二晶体管的第二栅极沟槽和对应于第三晶体管的第三栅极沟槽。 在内层电介质层上形成功函数金属层。 在功函数金属层上涂布抗反射层。 去除第二晶体管上的抗反射层和第三栅极沟槽的顶部以暴露功函数金属层。 暴露的功能金属层被去除。

公开(公告)号：US20140346616A1

公开(公告)日：2014-11-27

申请号：US14454727

申请日：2014-08-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Min-Chuan Tsai ,  Hsin-Fu Huang ,  Chi-Mao Hsu ,  Chin-Fu Lin ,  Chien-Hao Chen ,  Wei-Yu Chen ,  Chi-Yuan Sun ,  Ya-Hsueh Hsieh ,  Tsun-Min Cheng

IPC: H01L29/49 ,  H01L29/78 ,  H01L29/51

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4958 ,  H01L29/512 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure includes a work function metal layer, a (work function) metal oxide layer and a main electrode. The work function metal layer is located on a substrate. The (work function) metal oxide layer is located on the work function metal layer. The main electrode is located on the (work function) metal oxide layer. A semiconductor process forming said semiconductor structure is also provided.

Abstract translation: 半导体结构包括功函数金属层，（功函数）金属氧化物层和主电极。 功函数金属层位于基板上。 （功函数）金属氧化物层位于功函数金属层上。 主电极位于（功函数）金属氧化物层上。 还提供了形成所述半导体结构的半导体工艺。

公开(公告)号：US20140239419A1

公开(公告)日：2014-08-28

申请号：US13778227

申请日：2013-02-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Hao Chen ,  Hsin-Fu Huang ,  Chi-Yuan Sun ,  Min-Chuan Tsai ,  Wei-Yu Chen ,  Nien-Ting Ho ,  Tsun-Min Cheng ,  Chi-Mao Hsu

IPC: H01L29/423 ,  H01L29/40

CPC classification number: H01L29/401 ,  H01L21/28044 ,  H01L21/28185 ,  H01L29/4925 ,  H01L29/51

Abstract: A method of manufacturing a semiconductor device is provided. A silicon substrate is provided, and a gate insulating layer is formed on the silicon substrate. Then, a silicon barrier layer is formed on the gate insulating layer by the physical vapor deposition (PVD) process. Next, a silicon-containing layer is formed on the silicon barrier layer. The silicon barrier layer of the embodiment is a hydrogen-substantial-zero silicon layer, which has a hydrogen concentration of zero substantially.

Abstract translation: 提供一种制造半导体器件的方法。 提供硅衬底，并且在硅衬底上形成栅极绝缘层。 然后，通过物理气相沉积（PVD）工艺在栅极绝缘层上形成硅阻挡层。 接着，在硅阻隔层上形成含硅层。 本实施方式的硅阻隔层是基本上为氢的氢浓度为零的氢 - 实际为零的硅层。

公开(公告)号：US20240421213A1

公开(公告)日：2024-12-19

申请号：US18813074

申请日：2024-08-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Fu-Jung Chuang ,  Tsuo-Wen Lu ,  Chia-Ming Kuo ,  Po-Jen Chuang ,  Chi-Mao Hsu

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L29/78

Abstract: A semiconductor device includes a gate structure on a substrate, a first spacer on sidewalls of gate structure, a second spacer on sidewalls of the first spacer, a polymer block adjacent to the first spacer and on a corner between the gate structure and the substrate, an interfacial layer under the polymer block, and a source/drain region adjacent to two sides of the first spacer. Preferably, the polymer block is surrounded by the first spacer, the interfacial layer, and the second spacer.

公开(公告)号：US11508832B2

公开(公告)日：2022-11-22

申请号：US17209244

申请日：2021-03-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Fu-Jung Chuang ,  Tsuo-Wen Lu ,  Chia-Ming Kuo ,  Po-Jen Chuang ,  Chi-Mao Hsu

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H01L21/311

Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a polymer block on a corner between the gate structure and the substrate; performing a cleaning process; performing an oxidation process by injecting oxygen gas under 750° C. to form a first seal layer on sidewalls of the gate structure; and forming a source/drain region adjacent to two sides of the gate structure.

公开(公告)号：US10707214B2

公开(公告)日：2020-07-07

申请号：US15990837

申请日：2018-05-29

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chia-Chen Wu ,  Yi-Wei Chen ,  Chi-Mao Hsu ,  Kai-Jiun Chang ,  Chih-Chieh Tsai ,  Pin-Hong Chen ,  Tsun-Min Cheng ,  Yi-An Huang

IPC: H01L27/108 ,  C23C14/06 ,  C23C14/34 ,  C23C14/58 ,  H01L21/285

Abstract: A method of fabricating a cobalt silicide layer includes providing a substrate disposed in a chamber. A deposition process is performed to form a cobalt layer covering the substrate. The deposition process is performed when the temperature of the substrate is between 50° C. and 100° C., and the temperature of the chamber is between 300° C. and 350° C. After the deposition process, an annealing process is performed to transform the cobalt layer into a cobalt silicide layer. The annealing process is performed when the substrate is between 300° C. and 350° C., and the duration of the annealing process is between 50 seconds and 60 seconds.