公开(公告)号：US09530778B1

公开(公告)日：2016-12-27

申请号：US14834439

申请日：2015-08-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chao-Hung Lin ,  Chih-Kai Hsu ,  Li-Wei Feng ,  Shih-Hung Tsai ,  Chien-Ting Lin ,  Jyh-Shyang Jenq ,  Ching-Wen Hung ,  Jia-Rong Wu ,  Yi-Hui Lee ,  Ying-Cheng Liu ,  Yi-Kuan Wu ,  Chih-Sen Huang ,  Yi-Wei Chen

IPC: H01L21/00 ,  H01L27/092 ,  H01L29/51 ,  H01L21/8238

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/511 ,  H01L29/517

Abstract: Semiconductor devices having metal gate include a substrate, a first nFET device formed thereon, and a second nFET device formed thereon. The first nFET device includes a first n-metal gate, and the first n-metal gate includes a third bottom barrier metal layer and an n type work function metal layer. The n type work function metal layer directly contacts the third bottom barrier layer. The second nFET device includes a second n-metal gate and the second n-metal gate includes a second bottom barrier metal layer, the n type work function metal layer, and a third p type work function metal layer sandwiched between the second bottom barrier metal layer and the n type work function metal layer. The third p type work function metal layer of the second nFET device and the third bottom barrier metal layer of the first nFET device include a same material.

Abstract translation: 具有金属栅极的半导体器件包括衬底，其上形成的第一nFET器件和形成在其上的第二nFET器件。 第一nFET器件包括第一n型金属栅极，并且第一n型金属栅极包括第三底部阻挡金属层和n型功函数金属层。 n型功函数金属层直接接触第三底层阻挡层。 第二nFET器件包括第二n型金属栅极，第二n型金属栅极包括第二底部阻挡金属层，n型功函数金属层和夹在第二底部阻挡金属之间的第三p型功函数金属层 层和n型功函数金属层。 第二nFET器件的第三p型功函数金属层和第一nFET器件的第三底阻挡金属层包括相同的材料。

公开(公告)号：US20160260636A1

公开(公告)日：2016-09-08

申请号：US14672255

申请日：2015-03-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Ting Lin

IPC: H01L21/8234 ,  H01L29/78 ,  H01L21/762 ,  H01L29/06 ,  H01L21/306 ,  H01L21/308

CPC classification number: H01L21/823412 ,  H01L21/76232 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/66795

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region, a second region, and a third region defined thereon; forming a plurality of fin-shaped structures on the first region, the second region, and the third region of the substrate; performing a first fin-cut process to form a first fin-shaped structure on the first region, a second fin-shaped structure on the second region, and a third fin-shaped structure on the third region, wherein the height of the first fins-shaped structure is different from the heights of the second fin-shaped structure and the third fin-shaped structure; and performing a second fin-cut process to lower the height of the third fin-shaped structure.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供具有第一区域，第二区域和限定在其上的第三区域的衬底; 在所述基板的所述第一区域，所述第二区域和所述第三区域上形成多个鳍状结构; 执行第一切割处理以在第一区域上形成第一鳍状结构，在第二区域上形成第二鳍状结构，在第三区域上形成第三鳍​​状结构，其中第一鳍片 形结构与第二鳍状结构和第三鳍状结构的高度不同; 以及执行第二鳍片切割工艺以降低所述第三鳍状结构的高度。

公开(公告)号：US09312365B2

公开(公告)日：2016-04-12

申请号：US14487103

申请日：2014-09-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Hung Tsai ,  Ssu-I Fu ,  Ying-Tsung Chen ,  Chih-Wei Chen ,  Ying-Chih Lin ,  Chien-Ting Lin ,  Hsuan-Hsu Chen

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/78 ,  H01L29/51

CPC classification number: H01L29/66795 ,  H01L29/51 ,  H01L29/66818 ,  H01L29/785

Abstract: The present invention provides a non-planar FET which includes a substrate, a fin structure, a sub spacer, a gate, a dielectric layer and a source/drain region. The fin structure is disposed on the substrate. The sub spacer is disposed only on a middle sidewall of the fin structure. The gate is disposed on the fin structure. The dielectric layer is disposed between the fin structure and the gate. The source/drain region is disposed in the fin structure. The present invention further provides a method of forming the same.

Abstract translation: 本发明提供一种非平面FET，其包括基板，鳍结构，子间隔物，栅极，电介质层和源极/漏极区域。 翅片结构设置在基板上。 子间隔件仅设置在翅片结构的中间侧壁上。 门设置在翅片结构上。 介电层设置在翅片结构和栅极之间。 源/漏区设置在鳍结构中。 本发明还提供一种形成该方法的方法。

公开(公告)号：US09306032B2

公开(公告)日：2016-04-05

申请号：US14062909

申请日：2013-10-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Ling Lin ,  Chih-Sen Huang ,  Po-Chao Tsao ,  Ching-Wen Hung ,  Jia-Rong Wu ,  Chien-Ting Lin

IPC: H01L21/3205 ,  H01L29/66

CPC classification number: H01L29/66477 ,  H01L21/28247 ,  H01L21/76834 ,  H01L21/76897 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/7848

Abstract: A method for manufacturing a semiconductor device includes following steps. A substrate having at least a transistor embedded in an insulating material formed thereon is provided. The transistor includes a metal gate. Next, an etching process is performed to remove a portion of the metal gate to form a recess and to remove a portion of the insulating material to form a tapered part. After forming the recess and the tapered part of the insulating material, a hard mask layer is formed on the substrate to fill up the recess. Subsequently, the hard mask layer is planarized.

Abstract translation: 一种制造半导体器件的方法包括以下步骤。 提供了至少具有嵌入在其上形成绝缘材料的晶体管的衬底。 晶体管包括金属栅极。 接下来，进行蚀刻处理以去除金属栅极的一部分以形成凹部并且去除绝缘材料的一部分以形成锥形部分。 在形成凹部和绝缘材料的锥形部分之后，在基板上形成硬掩模层以填充凹部。 随后，硬掩模层被平坦化。

公开(公告)号：US09263540B1

公开(公告)日：2016-02-16

申请号：US14852624

申请日：2015-09-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Ling Lin ,  Chih-Sen Huang ,  Shih-Fang Tzou ,  Chien-Ting Lin ,  Yi-Wei Chen ,  Shi-Xiong Lin ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  Hsiao-Pang Chou ,  Chia-Lin Lu

IPC: H01L27/088 ,  H01L29/49 ,  H01L29/423

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/823456 ,  H01L21/82385 ,  H01L27/088 ,  H01L29/4232 ,  H01L29/517 ,  H01L29/66545

Abstract: The metal gate structure includes at least a substrate, a dielectric layer, first and second trenches, first metal layer and second metal layers, and two cap layers. In particular, the dielectric layer is disposed on the substrate, and the first and second trenches are disposed in the dielectric layer. The width of the first trench is less than the width of the second trench. The first and second metal layers are respectively disposed in the first trench and the second trench, and the height of the first metal layer is less than or equal to the height of the second metal layer. The cap layers are respectively disposed in a top surface of the first metal layer and a top surface of the second metal layer.

Abstract translation: 金属栅极结构至少包括衬底，电介质层，第一和第二沟槽，第一金属层和第二金属层以及两个盖层。 特别地，介电层设置在基板上，并且第一和第二沟槽设置在电介质层中。 第一沟槽的宽度小于第二沟槽的宽度。 第一和第二金属层分别设置在第一沟槽和第二沟槽中，第一金属层的高度小于或等于第二金属层的高度。 盖层分别设置在第一金属层的顶表面和第二金属层的顶表面中。

公开(公告)号：US09196546B2

公开(公告)日：2015-11-24

申请号：US14025833

申请日：2013-09-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Fang Tzou ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Hung-Yi Wu ,  Tong-Jyun Huang ,  Chien-Ting Lin ,  Chun-Hsien Lin

IPC: H01L29/76 ,  H01L21/8238

CPC classification number: H01L29/4966 ,  H01L21/823842 ,  H01L21/823864 ,  H01L29/42364 ,  H01L29/66545

Abstract: A metal gate transistor is disclosed. The metal gate transistor includes a substrate, a metal gate on the substrate, and a source/drain region in the substrate. The metal gate further includes a high-k dielectric layer, a bottom barrier metal (BBM) layer on the high-k dielectric layer, a first work function layer on the BBM layer, a second work function layer between the BBM layer and the first work function layer, and a low resistance metal layer on the first work function layer. Preferably, the first work function layer includes a p-type work function layer and the second work function layer includes a n-type work function layer.

Abstract translation: 公开了一种金属栅极晶体管。 金属栅极晶体管包括衬底，衬底上的金属栅极和衬底中的源极/漏极区域。 金属栅极还包括高k电介质层，高k电介质层上的底部阻挡金属（BBM）层，BBM层上的第一功函数层，BBM层和第一层之间的第二功函数层 功函数层，第一功函数层上的低电阻金属层。 优选地，第一功函数层包括p型功函数层，第二功函数层包括n型功函数层。

公开(公告)号：US09159798B2

公开(公告)日：2015-10-13

申请号：US13886382

申请日：2013-05-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jun-Jie Wang ,  Po-Chao Tsao ,  Chia-Jui Liang ,  Shih-Fang Tzou ,  Chien-Ting Lin ,  Cheng-Guo Chen ,  Ssu-I Fu ,  Yu-Hsiang Hung ,  Chung-Fu Chang

IPC: H01L21/8238 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/42364 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/7851

Abstract: A replacement gate process is disclosed. A substrate and a dummy gate structure formed on the substrate is provided, wherein the dummy gate structure comprises a dummy layer on the substrate, a hard mask layer on the dummy layer, spacers at two sides of the dummy layer and the hard mask layer, and a contact etch stop layer (CESL) covering the substrate, the spacers and the hard mask layer. The spacers and the CESL are made of the same material. Then, a top portion of the CESL is removed to expose the hard mask layer. Next, the hard mask layer is removed. Afterward, the dummy layer is removed to form a trench.

Abstract translation: 公开了替代浇口工艺。 提供了一种在基板上形成的基板和虚拟栅极结构，其中，虚设栅极结构包括基板上的虚设层，虚设层上的硬掩模层，虚设层两侧的间隔物和硬掩模层， 以及覆盖衬底，间隔物和硬掩模层的接触蚀刻停止层（CESL）。 垫片和CESL由相同的材料制成。 然后，去除CESL的顶部以露出硬掩模层。 接下来，去除硬掩模层。 之后，去除虚拟层以形成沟槽。

公开(公告)号：US20150118835A1

公开(公告)日：2015-04-30

申请号：US14062909

申请日：2013-10-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Ling Lin ,  Chih-Sen Huang ,  Po-Chao Tsao ,  Ching-Wen Hung ,  Jia-Rong Wu ,  Chien-Ting Lin

IPC: H01L21/768 ,  H01L29/66

CPC classification number: H01L29/66477 ,  H01L21/28247 ,  H01L21/76834 ,  H01L21/76897 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/7848

Abstract: A method for manufacturing a semiconductor device includes following steps. A substrate having at least a transistor embedded in an insulating material formed thereon is provided. The transistor includes a metal gate. Next, an etching process is performed to remove a portion of the metal gate to form a recess and to remove a portion of the insulating material to form a tapered part. After forming the recess and the tapered part of the insulating material, a hard mask layer is formed on the substrate to fill up the recess. Subsequently, the hard mask layer is planarized.

Abstract translation: 一种制造半导体器件的方法包括以下步骤。 提供了至少具有嵌入在其上形成绝缘材料的晶体管的衬底。 晶体管包括金属栅极。 接下来，进行蚀刻处理以去除金属栅极的一部分以形成凹部并且去除绝缘材料的一部分以形成锥形部分。 在形成凹部和绝缘材料的锥形部分之后，在基板上形成硬掩模层以填充凹部。 随后，硬掩模层被平坦化。

公开(公告)号：US09006091B2

公开(公告)日：2015-04-14

申请号：US14302047

申请日：2014-06-11

Applicant: United Microelectronics Corp.

Inventor： Shih-Hung Tsai ,  Ssu-I Fu ,  Ying-Tsung Chen ,  Chih-Wei Chen ,  Chien-Ting Lin ,  Wen-Tai Chiang

IPC: H01L21/338 ,  H01L29/66 ,  H01L21/283 ,  H01L21/28 ,  H01L21/762 ,  H01L29/78 ,  H01L29/51

CPC classification number: H01L29/6681 ,  H01L21/28088 ,  H01L21/28114 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/283 ,  H01L21/76224 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/785

Abstract: A method of forming a semiconductor device is provided. A first interfacial material layer is formed by a deposition process on a substrate. A dummy gate material layer is formed on the first interfacial material layer. The dummy gate material layer and the first interfacial material layer are patterned to form a stacked structure. An interlayer dielectric (ILD) layer is formed to cover the stacked structure. A portion of the ILD layer is removed to expose a top of the stacked structure. The stacked structure is removed to form a trench in the ILD layer. A second interfacial layer and a first high-k layer are conformally formed at least on a surface of the trench. A composite metal layer is formed to at least fill up the trench.

Abstract translation: 提供一种形成半导体器件的方法。 通过在衬底上的沉积工艺形成第一界面材料层。 在第一界面材料层上形成虚拟栅极材料层。 将虚拟栅材料层和第一界面材料层图案化以形成堆叠结构。 形成层间电介质（ILD）层以覆盖层叠结构。 去除ILD层的一部分以露出堆叠结构的顶部。 去除层叠结构以在ILD层中形成沟槽。 至少在沟槽的表面上共形地形成第二界面层和第一高k层。 复合金属层形成为至少填充沟槽。

公开(公告)号：US20150017781A1

公开(公告)日：2015-01-15

申请号：US13941208

申请日：2013-07-12

Applicant: United Microelectronics Corp.

Inventor： Chien-Ting Lin ,  Shih-Hung Tsai ,  Chun-Hsien Lin

IPC: H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/308 ,  H01L21/3086 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/845

Abstract: A method of forming a shallow trench isolation structure is disclosed. Hard mask patterns are formed on a substrate. A portion of the substrate is removed, using the hard mask patterns as a mask, to form first trenches in the substrate, wherein a fin is disposed between the neighboring first trenches. A filling layer is formed in the first trenches. A patterned mask layer is formed on the filling layer. A portion of the filling layer and a portion of the fins are removed, using the patterned mask layer as a mask, to form second trenches in the substrate. A first insulating layer is formed on the substrate filling in the second trenches.

Abstract translation: 公开了形成浅沟槽隔离结构的方法。 在基板上形成硬掩模图案。 使用硬掩模图案作为掩模去除衬底的一部分，以在衬底中形成第一沟槽，其中翅片设置在相邻的第一沟槽之间。 在第一沟槽中形成填充层。 在填充层上形成图案化掩模层。 使用图案化掩模层作为掩模，去除填充层的一部分和散热片的一部分，以在衬底中形成第二沟槽。 在填充在第二沟槽中的衬底上形成第一绝缘层。