公开(公告)号：US09870823B2

公开(公告)日：2018-01-16

申请号：US15596499

申请日：2017-05-16

Applicant: UNITY SEMICONDUCTOR CORPORATION

Inventor： Chang Hua Siau ,  Bruce Lynn Bateman

IPC: G11C11/00 ,  G11C13/00 ,  G11C5/06 ,  G11C5/08 ,  G11C7/00 ,  G11C7/04 ,  G11C7/12 ,  G11C7/18 ,  G11C16/24

CPC classification number: G11C5/06 ,  G11C5/08 ,  G11C7/00 ,  G11C7/04 ,  G11C7/12 ,  G11C7/18 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C16/24 ,  G11C2213/71

Abstract: A memory array includes wordlines, local bitlines, two-terminal memory elements, global bitlines, and local-to-global bitline pass gates and gain stages. The memory elements are formed between the wordlines and local bitlines. Each local bitline is selectively coupled to an associated global bitline, by way of an associated local-to-global bitline pass gate. During a read operation when a memory element of a local bitline is selected to be read, a local-to-global gain stage is configured to amplify a signal on or passing through the local bitline to an amplified signal on or along an associated global bitline. The amplified signal, which in one embodiment is dependent on the resistive state of the selected memory element, is used to rapidly determine the memory state stored by the selected memory element. The global bit line and/or the selected local bit line can be biased to compensate for the Process Voltage Temperature (PVT) variation.

公开(公告)号：US20160300883A1

公开(公告)日：2016-10-13

申请号：US15095542

申请日：2016-04-11

Applicant: Unity Semiconductor Corporation

Inventor： Bruce Lynn Bateman

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/249 ,  H01L27/2418 ,  H01L27/2454 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147

Abstract: An ultra-high-density vertical cross-point array comprises a plurality of horizontal line layers having horizontal lines interleaved with a plurality of vertical lines arranged in rows and columns. The vertical lines are interleaved with the horizontal lines such that a row of vertical lines is positioned between each consecutive pair of horizontal lines in each horizontal line layer. Each vertical line comprises a center conductor surrounded by a single or multi-layered memory film. Accordingly, when interleaved with the horizontal lines, two-terminal memory cells are integrally formed between the center conductor of each vertical line and each crossing horizontal line. By configuring the vertical and horizontal lines so that a row of vertical lines is positioned between each consecutive pair of horizontal lines, a unit memory cell footprint of just 2F2 may be realized.

Abstract translation: 超高密度垂直交叉点阵列包括多个水平线层，水平线与以行和列排列的多条垂直线交错。 垂直线与水平线交错，使得一行垂直线位于每条水平线层中每条连续的一对水平线之间。 每个垂直线包括由单层或多层记忆膜包围的中心导体。 因此，当与水平线交错时，两端存储单元一体地形成在每条垂直线的中心导体和每个交叉水平线之间。 通过配置垂直和水平线，使得一行垂直线位于每条连续的一对水平线之间，可以实现仅仅2F2的单位存储单元占用空间。

公开(公告)号：US09368200B2

公开(公告)日：2016-06-14

申请号：US14254209

申请日：2014-04-16

Applicant: Unity Semiconductor Corporation

Inventor： Bruce Lynn Bateman ,  Christophe Chevallier ,  Darrell Rinerson ,  Chang Hua Siau

IPC: G11C7/00 ,  G11C13/00 ,  G11C7/12 ,  G11C7/22

CPC classification number: G11C13/004 ,  G11C7/12 ,  G11C7/22 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0009 ,  G11C13/0011 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0045 ,  G11C2013/0054 ,  G11C2213/11 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/53 ,  G11C2213/71 ,  G11C2213/77

Abstract: A low read current architecture for memory. Bit lines of a cross point memory array are allowed to be charged by a selected word line until a minimum voltage differential between a memory state and a reference level is assured.

公开(公告)号：US20140334222A1

公开(公告)日：2014-11-13

申请号：US14254209

申请日：2014-04-16

Applicant: Unity Semiconductor Corporation

Inventor： Bruce Lynn Bateman ,  Christophe Chevallier ,  Darrell Rinerson ,  Chang Hua Siau

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C7/12 ,  G11C7/22 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0009 ,  G11C13/0011 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0045 ,  G11C2013/0054 ,  G11C2213/11 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/53 ,  G11C2213/71 ,  G11C2213/77

Abstract: A low read current architecture for memory. Bit lines of a cross point memory array are allowed to be charged by a selected word line until a minimum voltage differential between a memory state and a reference level is assured.

Abstract translation: 用于存储器的低读取当前体系结构。 允许交叉点存储器阵列的位线被选择的字线充电，直到确保存储器状态和参考电平之间的最小电压差。

公开(公告)号：US10790334B2

公开(公告)日：2020-09-29

申请号：US15633050

申请日：2017-06-26

Applicant: Unity Semiconductor Corporation

Inventor： Bruce Lynn Bateman

IPC: H01L45/00 ,  H01L27/24

Abstract: An ultra-high-density vertical cross-point array comprises a plurality of horizontal line layers having horizontal lines interleaved with a plurality of vertical lines arranged in rows and columns. The vertical lines are interleaved with the horizontal lines such that a row of vertical lines is positioned between each consecutive pair of horizontal lines in each horizontal line layer. Each vertical line comprises a center conductor surrounded by a single or multi-layered memory film. Accordingly, when interleaved with the horizontal lines, two-terminal memory cells are integrally formed between the center conductor of each vertical line and each crossing horizontal line. By configuring the vertical and horizontal lines so that a row of vertical lines is positioned between each consecutive pair of horizontal lines, a unit memory cell footprint of just 2F2 may be realized.

公开(公告)号：US20180366194A9

公开(公告)日：2018-12-20

申请号：US15868234

申请日：2018-01-11

Applicant: Unity Semiconductor Corporation

Inventor： Chang Hua Siau ,  Bruce Lynn Bateman

IPC: G11C13/00 ,  G11C16/24 ,  G11C5/06 ,  G11C5/08 ,  G11C7/00 ,  G11C7/04 ,  G11C7/12 ,  G11C7/18

CPC classification number: G11C13/0069 ,  G11C5/06 ,  G11C5/08 ,  G11C7/00 ,  G11C7/04 ,  G11C7/12 ,  G11C7/18 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/004 ,  G11C13/0097 ,  G11C16/24 ,  G11C2213/71

Abstract: A memory array includes wordlines, local bitlines, two-terminal memory elements, global bitlines, and local-to-global bitline pass gates and gain stages. The memory elements are formed between the wordlines and local bitlines. Each local bitline is selectively coupled to an associated global bitline, by way of an associated local-to-global bitline pass gate. During a read operation when a memory element of a local bitline is selected to be read, a local-to-global gain stage is configured to amplify a signal on or passing through the local bitline to an amplified signal on or along an associated global bitline. The amplified signal, which in one embodiment is dependent on the resistive state of the selected memory element, is used to rapidly determine the memory state stored by the selected memory element. The global bit line and/or the selected local bit line can be biased to compensate for the Process Voltage Temperature (PVT) variation.

公开(公告)号：US09691480B2

公开(公告)日：2017-06-27

申请号：US15205882

申请日：2016-07-08

Applicant: UNITY SEMICONDUCTOR CORPORATION

Inventor： Chang Hua Siau ,  Bruce Lynn Bateman

IPC: G11C11/00 ,  G11C13/00 ,  G11C5/06 ,  G11C5/08 ,  G11C7/00 ,  G11C7/18 ,  G11C7/04 ,  G11C7/12 ,  G11C16/24

CPC classification number: G11C5/06 ,  G11C5/08 ,  G11C7/00 ,  G11C7/04 ,  G11C7/12 ,  G11C7/18 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C16/24 ,  G11C2213/71

Abstract: A memory array includes wordlines, local bitlines, two-terminal memory elements, global bitlines, and local-to-global bitline pass gates and gain stages. The memory elements are formed between the wordlines and local bitlines. Each local bitline is selectively coupled to an associated global bitline, by way of an associated local-to-global bitline pass gate. During a read operation when a memory element of a local bitline is selected to be read, a local-to-global gain stage is configured to amplify a signal on or passing through the local bitline to an amplified signal on or along an associated global bitline. The amplified signal, which in one embodiment is dependent on the resistive state of the selected memory element, is used to rapidly determine the memory state stored by the selected memory element. The global bit line and/or the selected local bit line can be biased to compensate for the Process Voltage Temperature (PVT) variation.

公开(公告)号：US09570459B2

公开(公告)日：2017-02-14

申请号：US14314622

申请日：2014-06-25

Applicant: Unity Semiconductor Corporation

Inventor： Bruce Lynn Bateman

IPC: H01L29/76 ,  H01L27/115 ,  H01L29/66 ,  H01L29/792 ,  G11C16/04 ,  G11C16/34

CPC classification number: H01L27/11582 ,  G11C16/0483 ,  G11C16/3418 ,  H01L27/11551 ,  H01L27/11578 ,  H01L29/66833 ,  H01L29/7926

Abstract: In an example, a device comprises a vertical stack of memory cells. Each memory cell of the vertical stack may include more than one memory element. A first vertical gate line may be coupled to a first one of the memory elements in each memory cell, and a second vertical gate line may be coupled to a second one of the memory elements in each memory cell. The first vertical gate line may be electrically isolated from the second vertical gate line.

Abstract translation: 在一个示例中，设备包括垂直堆叠的存储器单元。 垂直堆栈的每个存储单元可以包括多于一个存储元件。 第一垂直栅极线可以耦合到每个存储器单元中的存储器元件中的第一个，并且第二垂直栅极线可以耦合到每个存储器单元中的第二个存储器元件。 第一垂直栅极线可以与第二垂直栅极线电隔离。

公开(公告)号：US09312307B2

公开(公告)日：2016-04-12

申请号：US14568802

申请日：2014-12-12

Applicant: UNITY SEMICONDUCTOR CORPORATION

Inventor： Bruce Lynn Bateman

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L27/249 ,  H01L27/2418 ,  H01L27/2454 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147

Abstract: An ultra-high-density vertical cross-point array comprises a plurality of horizontal line layers having horizontal lines interleaved with a plurality of vertical lines arranged in rows and columns. The vertical lines are interleaved with the horizontal lines such that a row of vertical lines is positioned between each consecutive pair of horizontal lines in each horizontal line layer. Each vertical line comprises a center conductor surrounded by a single or multi-layered memory film. Accordingly, when interleaved with the horizontal lines, two-terminal memory cells are integrally formed between the center conductor of each vertical line and each crossing horizontal line. By configuring the vertical and horizontal lines so that a row of vertical lines is positioned between each consecutive pair of horizontal lines, a unit memory cell footprint of just 2F2 may be realized.

公开(公告)号：US20220392956A1

公开(公告)日：2022-12-08

申请号：US17840385

申请日：2022-06-14

Applicant: Unity Semiconductor Corporation

Inventor： Bruce Lynn Bateman

IPC: H01L27/24 ,  H01L45/00

Abstract: An ultra-high-density vertical cross-point array comprises a plurality of horizontal line layers having horizontal lines interleaved with a plurality of vertical lines arranged in rows and columns. The vertical lines are interleaved with the horizontal lines such that a row of vertical lines is positioned between each consecutive pair of horizontal lines in each horizontal line layer. Each vertical line comprises a center conductor surrounded by a single or multi-layered memory film. Accordingly, when interleaved with the horizontal lines, two-terminal memory cells are integrally formed between the center conductor of each vertical line and each crossing horizontal line. By configuring the vertical and horizontal lines so that a row of vertical lines is positioned between each consecutive pair of horizontal lines, a unit memory cell footprint of just 2F2 may be realized.