公开(公告)号：US20210398985A1

公开(公告)日：2021-12-23

申请号：US17340507

申请日：2021-06-07

Applicant: Winbond Electronics Corp.

Inventor： Wei-Che CHANG ,  Kai JEN ,  Yu-Po WANG

IPC: H01L27/108

Abstract: A semiconductor structure includes a semiconductor substrate and an isolation structure disposed in the semiconductor substrate. The isolation structure includes a lining layer disposed along a boundary between the semiconductor substrate and the isolation structure, a first oxide fill layer disposed over the lining layer, a dielectric barrier structure surrounding the first oxide fill layer in a closed loop, and a second oxide fill layer disposed over the dielectric barrier structure and adjacent to the lining layer.

公开(公告)号：US20210210376A1

公开(公告)日：2021-07-08

申请号：US17140627

申请日：2021-01-04

Applicant: Winbond Electronics Corp.

Inventor： Hao Chuan CHANG ,  Kai JEN

IPC: H01L21/762

Abstract: A semiconductor structure and its manufacturing method are provided. The semiconductor structure includes a substrate having a trench. The semiconductor structure also includes an oxide layer conformally formed in the trench and a protective layer formed in the trench. Also, the protective layer is conformally formed on the oxide layer. The semiconductor structure further includes an insulating material layer in the trench, and the insulating material layer is formed above the protective layer, wherein a top surface of the insulating material layer is higher than a top surface of the protective layer.

公开(公告)号：US20200335506A1

公开(公告)日：2020-10-22

申请号：US16389322

申请日：2019-04-19

Applicant: Winbond Electronics Corp.

Inventor： Yi-Hao CHIEN ,  Kazuaki TAKESAKO ,  Kai JEN ,  Hung-Yu WEI

IPC: H01L27/108

Abstract: A semiconductor device and a manufacturing method of the same are provided. The method includes forming a plurality of first conductive structures and a first dielectric layer between the first conductive structures on a substrate. The method also includes forming a trench between the first dielectric layer and the first conductive structures. The method further includes forming a liner material on a sidewall and a bottom of the trench. In addition, the method includes forming a conductive plug on the liner material in the trench. The method also includes removing the liner material to form an air gap, and the air gap is located between the conductive plug and the first dielectric layer.

公开(公告)号：US20200312856A1

公开(公告)日：2020-10-01

申请号：US16575734

申请日：2019-09-19

Applicant: Winbond Electronics Corp.

Inventor： Kai JEN ,  Shou-Te WANG

IPC: H01L27/108

Abstract: The memory structure includes a substrate, an isolation structure disposed in the substrate; a word line trench; and a word line disposed in the word line trench. The word line has an upper gate and a lower gate. The upper gate includes an upper gate dielectric layer; an upper gate liner disposed on the upper gate dielectric layer; and an upper gate electrode disposed on the upper gate liner. The lower gate includes a lower gate dielectric layer; a lower gate liner disposed on the lower gate dielectric layer; and a lower gate electrode disposed on the lower gate liner. The vertical distance between the top surface of the upper gate dielectric layer and the bottom surface of the word line trench is not greater than that between the top surface of the upper gate electrode and the bottom surface of the word line trench.