公开(公告)号：US20250098156A1

公开(公告)日：2025-03-20

申请号：US18966744

申请日：2024-12-03

Applicant: Winbond Electronics Corp.

Inventor： Wei-Che CHANG ,  Kai JEN ,  Yu-Po WANG

IPC: H10B12/00

Abstract: A method for forming a semiconductor structure includes the following steps. A first trench is formed in a semiconductor substrate, and a first nitride layer is formed along a sidewall and a bottom surface of the first trench. A first oxide layer is formed over the first nitride layer to fill the first trench, and the first oxide layer is recessed from the first trench to form a first recess. A portion of the first nitride layer exposed from the first recess is etched, and a second nitride layer is formed along a sidewall and a bottom surface of the first recess. The second nitride layer includes a first portion along the bottom surface and a second portion along the sidewall. The second portion is removed, and a second oxide layer is formed over the first portion to fill the first recess.

公开(公告)号：US20210398985A1

公开(公告)日：2021-12-23

申请号：US17340507

申请日：2021-06-07

Applicant: Winbond Electronics Corp.

Inventor： Wei-Che CHANG ,  Kai JEN ,  Yu-Po WANG

IPC: H01L27/108

Abstract: A semiconductor structure includes a semiconductor substrate and an isolation structure disposed in the semiconductor substrate. The isolation structure includes a lining layer disposed along a boundary between the semiconductor substrate and the isolation structure, a first oxide fill layer disposed over the lining layer, a dielectric barrier structure surrounding the first oxide fill layer in a closed loop, and a second oxide fill layer disposed over the dielectric barrier structure and adjacent to the lining layer.

公开(公告)号：US20240321628A1

公开(公告)日：2024-09-26

申请号：US18476754

申请日：2023-09-28

Applicant: Winbond Electronics Corp.

Inventor： Yu-Po WANG ,  Te-Hsuan PENG

IPC: H01L21/768 ,  H01L21/027 ,  H01L21/033 ,  H01L21/8234

CPC classification number: H01L21/76802 ,  H01L21/0274 ,  H01L21/0332 ,  H01L21/823468

Abstract: A method for forming semiconductor structures is provided. The method includes forming a first patterning photoresist layer having a first opening on a first patterning layer, trimming the first patterning photoresist layer, transferring the first pattern of the trimmed first patterning photoresist layer to the first patterning layer, performing a first pattern reversal process to reverse the first pattern of the first patterning layer into the second opening, forming a second patterning layer in and on the second opening, forming a second patterning photoresist layer having a third opening on the second patterning layer, transferring the second pattern of the second patterning photoresist layer to a first stacking layer, performing a second pattern reversal process to reverse a third pattern between the second opening and the third opening into a fourth opening, and extending the fourth opening to the substrate.

公开(公告)号：US20220238526A1

公开(公告)日：2022-07-28

申请号：US17160871

申请日：2021-01-28

Applicant: Winbond Electronics Corp.

Inventor： Yu-Po WANG ,  Yi-Hao CHIEN ,  Hsiang-Po LIU

IPC: H01L27/108 ,  H01L29/06

Abstract: A semiconductor memory structure includes a semiconductor substrate including an active region and a chop region. The semiconductor memory structure also includes an isolation structure disposed in the chop region, a first gate structure extending at least through the isolation structure in the chop region, and a second gate structure extending at least through the active region. The semiconductor memory structure also includes a doped region disposed in the active region. A first distance between the doped region and the first gate structure is shorter than a second distance between the doped region and the second gate structure.