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    Conductive Through-Polymer Vias for Capacitative Structures Integrated with Packaged Semiconductor Chips
    12.
    发明申请
    Conductive Through-Polymer Vias for Capacitative Structures Integrated with Packaged Semiconductor Chips 有权
    与封装半导体芯片集成的电容式结构的导电聚合物通孔

    公开(公告)号：US20160286654A1

    公开(公告)日：2016-09-29

    申请号：US14668085

    申请日：2015-03-25

    Applicant: Texas Instruments Incorporated

    Inventor： Matthew D. Romig ,  Frank Stepniak ,  Saumya Gandhi

    IPC: H05K1/18

    CPC classification number: H01L23/5223 ,  H01L21/288 ,  H01L21/31051 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76874 ,  H01L21/76877 ,  H01L21/78 ,  H01L23/5226 ,  H01L23/528 ,  H01L24/14 ,  H01L28/60 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19104 ,  H05K1/113 ,  H05K1/162 ,  H05K1/181 ,  H05K1/185 ,  H05K2201/0187 ,  H05K2201/0215 ,  H05K2201/10734

    Abstract: An electronic system comprising an electronic body (301) with terminal pads (310) and at least one capacitor embedded in the electronic body. The capacitor including an insulating and adhesive first polymeric film (302) covering the body surface except the terminal pads; a sheet (320) of high-density capacitive elements, the first capacitor terminal being a metal foil (321) attached to film (302), the second terminal a conductive polymeric compound (324), and the insulator a dielectric skin (323). Sheet (320) has sets of via holes: the first set holes reaching metal foil 321), the second set holes reaching the terminals (310), and the third set holes reaching the conductive polymeric compound (324). An insulating second polymeric film (303) lining the sidewalls of the holes and planarizing the sheet surface; and metal (432) filling the via holes between the polymeric sidewalls and forming conductive traces and attachment pads on the system surface.

    Abstract translation: 一种电子系统，包括具有端子焊盘（310）的电子体（301）和嵌入电子体中的至少一个电容器。 所述电容器包括绝缘和粘合的第一聚合物膜（302），所述绝缘和粘合的第一聚合物膜（302）覆盖除了所述端子焊盘之外 高密度电容元件的片材（320），所述第一电容器端子是附着到膜（302）上的金属箔（321），所述第二端子是导电聚合物（324），所述绝缘体是介电性皮层（323） 。 片（320）具有一组通孔：第一组孔到达金属箔321），第二组孔到达端子（310），第三组孔到达导电聚合物（324）。 绝缘的第二聚合物膜（303），其衬在所述孔的侧壁上并平坦化所述片材表面; 和填充聚合物侧壁之间的通孔的金属（432），并在系统表面上形成导电迹线和附着垫。

    Lead-free solder paste
    17.
    发明授权
    Lead-free solder paste 有权
    无铅锡膏

    公开(公告)号：US09185812B2

    公开(公告)日：2015-11-10

    申请号：US11920962

    申请日：2006-05-24

    Applicant: Minoru Ueshima

    Inventor： Minoru Ueshima

    IPC: B23K35/26 ,  B23K35/22 ,  B23K35/00 ,  H05K3/34 ,  B23K35/02 ,  B23K35/362

    CPC classification number: H05K3/3484 ,  B23K35/0244 ,  B23K35/025 ,  B23K35/22 ,  B23K35/262 ,  B23K35/362 ,  H05K2201/0215 ,  H05K2201/0257

    Abstract: In a conventional Sn—Zn based lead-free solder, Zn crystallized to a large size of several tens of micrometers, and it was difficult to suppress the formation of coarse crystallizates and to increase the bonding strength without changing the soldering temperature. There were alloys which improved strength by the addition of a minute amount of a Group 1B metal, but the alloys had an increased melting temperature so that reflow could not be performed with the same temperature profile as for Sn—Pb, so the alloys had advantages and disadvantages.By using a solder paste formed by mixing an ethanol solution containing nanoparticles having a particle diameter of 5-300 nm and containing at least one of Ag, Au, and Cu with a flux and solder powder for an Sn—Zn based lead-free solder paste, the formation of an alloy of Au, Au, or Cu with Zn occurs during soldering, thereby forming fine clusters in the resulting liquid phase of molten solder, and a fine solder structure is obtained following melting.

    Abstract translation: 在常规的Sn-Zn基无铅焊料中，Zn结晶到几十微米的大尺寸，并且难以抑制粗结晶的形成，并且在不改变焊接温度的情况下提高接合强度。 存在通过添加少量1B族金属来提高强度的合金，但是合金具有增加的熔融温度，使得不能以与Sn-Pb相同的温度分布进行回流，因此合金具有优点 和缺点。 通过使用通过将含有粒径为5-300nm并含有Ag，Au和Cu中的至少一种的纳米颗粒的乙醇溶液与用于Sn-Zn基无铅焊料的助焊剂和焊料粉末混合而形成的焊膏 在焊接中发生Au，Au或Cu与Zn的合金的形成，从而在熔融焊料的液相中形成微细的簇，熔融后得到细小的焊料结构。

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