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11.发明申请COPPER CLAD LAMINATE PROVIDED WITH PROTECTIVE LAYER AND MULTILAYERED PRINTED WIRING BOARD 审中-公开具有保护层和多层印刷接线板的铜箔层压板公开(公告)号：US20160360624A1
公开(公告)日：2016-12-08
申请号：US15111315
申请日：2015-02-19
Applicant: MITSUI MINING & SMELTING CO., LTD.
Inventor： Fujio KUWAKO , Toshifumi MATSUSHIMA , Toshihiro HOSOI , Ayumu TATEOKA
CPC classification number: H05K3/4626 , H05K1/0298 , H05K1/09 , H05K3/022 , H05K3/429 , H05K2201/0187 , H05K2201/09645
Abstract: An object of the present invention is to provide a multilayered printed wiring board provided with split through holes excellent in through-hole formability and co-planarity in inner layer wirings around through holes for providing of a conduction isolation portion. To achieve the object, “a copper clad laminate provided with a protective layer for manufacturing of a printed wiring board having a conduction isolation portion electrically isolating a through hole, the copper clad laminate is characterized in that the copper clad laminate is provided with a protective layer on the surface that can be released after forming of the through holes for providing of a conduction isolation portion and filling of the through holes for providing of a conduction isolation portion by a plating resist” is employed.
Abstract translation: 本发明的目的是提供一种多层印刷电路板，其设置有通孔形成性优良的共通孔和用于提供导电隔离部分的通孔周围的内层布线的共通孔。 为了实现该目的，“覆铜层压板设置有用于制造具有电隔离通孔的导电隔离部分的印刷线路板的保护层的铜包覆层压板，其特征在于，覆铜层压板设置有保护层 在形成用于提供导电隔离部分的通孔和填充用于通过电镀抗蚀剂提供导电隔离部分的通孔之后可以释放的表面上的层。
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12.发明申请公开(公告)号：US20160174359A1
公开(公告)日：2016-06-16
申请号：US14570701
申请日：2014-12-15
Inventor： CANDICE L. COLETRANE , BRADLEY D. HERRMAN
CPC classification number: H05K1/0251 , H03H7/38 , H05K1/0222 , H05K1/0245 , H05K1/115 , H05K2201/09645 , H05K2201/09809
Abstract: A printed circuit board (‘PCB’) comprising: an interior socket configured to receive a connector pin of a first electronic component, the connector pin characterized by a pin impedance; a signal trace coupled to the interior socket, the signal trace configured to transmit electrical signals between the first electronic component and other electronic components mounted on the PCB, the signal trace characterized by a trace impedance; and an insulator between the interior socket and a sleeve that surrounds the interior socket, the sleeve physically configured such that an effective pin impedance matches the trace impedance within a predetermined threshold, wherein the effective pin impedance represents the resistance experienced by electrical signals passing through the connector pin when the connector pin is inserted into the interior socket.
Abstract translation: 一种印刷电路板（“PCB”），包括：内部插座，其被配置为接收第一电子部件的连接器插脚，所述连接器插脚的特征在于引脚阻抗; 耦合到所述内部插座的信号迹线，所述信号迹线被配置为在所述第一电子部件和安装在所述PCB上的其他电子部件之间传输电信号，所述信号迹线以迹线阻抗为特征; 以及在所述内部插座和套筒之间的绝缘体，所述绝缘体围绕所述内部插座，所述套管被物理地配置为使得有效引脚阻抗匹配在预定阈值内的迹线阻抗，其中所述有效引脚阻抗表示通过 连接器针脚插入内部插座时。
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公开(公告)号：US20160021762A1
公开(公告)日：2016-01-21
申请号：US14387928
申请日：2014-05-20
Applicant: Telefonaktiebolaget L M Ericsson (publ)
Inventor： Stig Kallman , Tomas Bergsten
CPC classification number: H05K3/429 , C25D5/02 , C25D5/022 , H05K1/092 , H05K1/115 , H05K2201/0187 , H05K2201/09645 , H05K2203/0713
Abstract: The embodiments herein relate to a method for selective partitioning of a via in a printed circuit board as to produce an electrically isolating portion between two electrically conducting portions in said via. The method involves the step of prior to drilling the hole for the via, laminating plating resist layers to the printed circuit board at a distance from each other corresponding to a desired length of the electrically isolated portion of the via. After drilling, copper is added to selected portions of the interior of the via in two different processing steps followed by a step of removing undesired copper as to produce the electrically isolating portion.
Abstract translation: 本文的实施例涉及用于在印刷电路板中选择性地分隔通孔以在所述通孔中的两个导电部分之间产生电绝缘部分的方法。 该方法包括以下步骤：在通孔之间钻孔，将电镀抗蚀剂层层压到与印刷电路板相隔一定距离的孔中，对应于通孔的电隔离部分的期望长度。 在钻孔之后，在两个不同的处理步骤中将铜加入到通孔内部的选定部分，接着是去除不需要的铜以产生电绝缘部分的步骤。
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14.发明授权Integrated circuit structures having off-axis in-hole capacitor and methods of forming 有权具有离轴孔隙电容器的集成电路结构及其形成方法公开(公告)号：US09078373B1
公开(公告)日：2015-07-07
申请号：US14147225
申请日：2014-01-03
Applicant: International Business Machines Corporation
Inventor： Mark C. Lamorey , Janak G. Patel , Peter Slota, Jr. , David B. Stone
CPC classification number: H05K1/183 , H05K1/0231 , H05K1/11 , H05K1/181 , H05K1/184 , H05K2201/09645 , H05K2201/10015 , H05K2201/10507 , Y02P70/611 , Y10T29/49135
Abstract: Various embodiments include integrated circuit structures having an off-axis in-hole capacitor. In some embodiments, an integrated circuit (IC) structure includes: a substrate layer having an upper surface; an IC chip at least partially contained within the substrate layer and aligned with a minor axis perpendicular to the upper surface of the substrate layer; an aperture in the substrate layer, the aperture physically separated from the IC chip; and a capacitor in the aperture and at least partially contained within the substrate layer, the capacitor being physically isolated from the IC chip, wherein the capacitor is aligned with an axis perpendicular to the upper surface of the substrate layer and offset from the minor axis of the IC chip.
Abstract translation: 各种实施例包括具有离轴孔内电容器的集成电路结构。 在一些实施例中，集成电路（IC）结构包括：具有上表面的基底层; 至少部分地包含在所述衬底层内并与垂直于所述衬底层的上表面的短轴对准的IC芯片; 所述基板层中的孔，所述孔与所述IC芯片物理分离; 以及孔中的电容器，并且至少部分地包含在所述衬底层内，所述电容器与所述IC芯片物理隔离，其中所述电容器与垂直于所述衬底层的上表面的轴线对准，并且偏离所述衬底层的短轴 IC芯片。
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公开(公告)号：US20150008029A1
公开(公告)日：2015-01-08
申请号：US14063053
申请日：2013-10-25
Applicant: BOARDTEK ELECTRONICS CORPORATION
Inventor： CHIEN-CHENG LEE
CPC classification number: H05K1/115 , H05K1/0251 , H05K1/0293 , H05K3/0094 , H05K3/429 , H05K2201/0959 , H05K2201/09645 , H05K2201/09845 , H05K2203/175 , Y10T29/49165
Abstract: A circuit board includes a substrate and a through via. The substrate has a first surface and a second surface opposite to the first surface. The substrate includes circuit layers and insulation layers. The insulation layers are sandwiched between the circuit layers. The through via goes through the substrate and has portions defining a first portion and a second portion. The first portion of the through via is coated with a first metal layer and electrically connected to at least one of the circuit layer by the first metal layer. The second portion of the through via is coated with a second metal layer and electrically connected to at least one of the circuit layer by the second metal layer. The first and second portions are electrically insulted, and the diameter of the second portion is larger than that of the first portion.
Abstract translation: 电路板包括基板和通孔。 基板具有与第一表面相对的第一表面和第二表面。 基板包括电路层和绝缘层。 绝缘层夹在电路层之间。 通孔穿过基板并且具有限定第一部分和第二部分的部分。 通孔的第一部分涂覆有第一金属层，并且通过第一金属层电连接到电路层中的至少一个。 通孔的第二部分被涂覆有第二金属层，并且通过第二金属层电连接到电路层中的至少一个。 第一部分和第二部分被电绝缘，并且第二部分的直径大于第一部分的直径。
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Patent Agency Ranking
公开(公告)号：US20140262455A1
公开(公告)日：2014-09-18
申请号：US14205331
申请日：2014-03-11
Applicant: SANMINA CORPORATION
Inventor： Shinichi Iketani , Dale Kersten
CPC classification number: H05K3/429 , H05K1/0251 , H05K1/115 , H05K2201/0187 , H05K2201/09536 , H05K2201/09645 , H05K2203/061 , H05K2203/0713 , Y10T29/49165
Abstract: A multilayer printed circuit board is provided having a first dielectric layer and a first plating resist selectively positioned in the first dielectric layer. A second plating resist may be selectively positioned in the first dielectric layer or a second dielectric layer, the second plating resist separate from the first plating resist. A through hole extends through the first dielectric layer, the first plating resist, and the second plating resist. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.
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17.发明申请Extrusion Process for Manufacturing a Z-Directed Component for a Printed Circuit Board 审中-公开用于制造用于印刷电路板的Z定向部件的挤出工艺公开(公告)号：US20140237816A1
公开(公告)日：2014-08-28
申请号：US14268265
申请日：2014-05-02
Applicant: LEXMARK INTERNATIONAL, INC.
Inventor： Paul Kevin Hall , Keith Bryan Hardin , Zachary Charles Nathan Kratzer , Qing Zhang
IPC: H05K3/10
CPC classification number: H05K3/108 , H05K1/0231 , H05K1/0233 , H05K1/0248 , H05K1/0251 , H05K1/184 , H05K3/4046 , H05K2201/09645 , Y10T29/49105 , Y10T29/49117 , Y10T29/49124 , Y10T29/49139 , Y10T29/49155 , Y10T29/49158 , Y10T29/49204
Abstract: A method for manufacturing a Z-directed component for insertion into a mounting hole in a printed circuit board according to one example embodiment includes extruding a substrate material according to the shape of the Z-directed component. A conductive material is then selectively applied to the extruded substrate material and the Z-directed component is formed from the extruded substrate material.
Abstract translation: 根据一个示例实施例的用于制造用于插入到印刷电路板的安装孔中的Z定向部件的方法包括根据Z指向部件的形状挤出基底材料。 然后将导电材料选择性地施加到挤出的基底材料上，并且由挤出的基底材料形成Z指向的部件。
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公开(公告)号：US20140190733A1
公开(公告)日：2014-07-10
申请号：US14123076
申请日：2012-10-29
Applicant: Peking University Founder Group Co., Ltd. , Zhuhai Founder PCB Development Co., Ltd. , Chongqing Gounder Hi-Tech Electronic Inc.
Inventor： George Dudnikov, JR. , Xinhong Su , Shuhan Shi
CPC classification number: H05K1/0298 , H05K1/0296 , H05K1/116 , H05K3/429 , H05K2201/09645 , H05K2201/09718 , Y10T29/49165
Abstract: Embodiments of the present application relate to the technical field of a printed circuit plate, in particular, to a printed circuit plate and a method manufacturing same so as to resolve a problem of an incomplete elimination of a short-line effect. The method for manufacturing a printed circuit board in the embodiments of the present application comprises a step of drilling target prepregs at positions corresponding to at least one preset hole therein so as to form through holes perforating through the target prepregs, wherein the formed through holes have an aperture greater than that of the preset hole, and the preset hole does not need to transmit electrical signal between layers of the PCB. The method further comprises: filling the formed through holes with a plating resist ink to prevent the through holes from being plated with a conductive material; laminating the target prepregs and core boards so as to form a multi-layer printed circuit board PCB, wherein some or all of the prepregs are the target prepregs; drilling the multi-layer PCB to perforate the preset holes in the target prepregs; and plating inner walls of holes formed by drilling the multi-layer PCB.
Abstract translation: 本申请的实施例涉及印刷电路板的技术领域，特别是印刷电路板及其制造方法，以解决不完全消除短线效应的问题。 在本申请的实施方式中，印刷电路板的制造方法包括在与其中的至少一个预定孔相对应的位置钻孔目标预浸料，以形成穿过目标预浸料穿孔的通孔，其中形成的通孔具有 孔径大于预设孔的孔径，并且预设孔不需要在PCB的层之间传输电信号。 该方法还包括：用电镀抗蚀剂油墨填充所形成的通孔，以防止通孔镀有导电材料; 层叠目标半固化片和芯板以形成多层印刷电路板PCB，其中部分或全部预浸料是目标预浸料; 钻多层PCB以穿孔目标预浸料的预设孔; 并对通过钻多层PCB形成的孔的内壁进行电镀。
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19.发明授权Extrusion process for manufacturing a Z-directed component for a printed circuit board 有权用于制造用于印刷电路板的Z定向部件的挤出工艺公开(公告)号：US08752280B2
公开(公告)日：2014-06-17
申请号：US13250812
申请日：2011-09-30
Applicant: Keith Bryan Hardin
Inventor： Keith Bryan Hardin
CPC classification number: H05K3/108 , H05K1/0231 , H05K1/0233 , H05K1/0248 , H05K1/0251 , H05K1/184 , H05K3/4046 , H05K2201/09645 , Y10T29/49105 , Y10T29/49117 , Y10T29/49124 , Y10T29/49139 , Y10T29/49155 , Y10T29/49158 , Y10T29/49204
Abstract: A method for manufacturing a Z-directed component for insertion into a mounting hole in a printed circuit board according to one example embodiment includes extruding a substrate material according to the shape of the Z-directed component. A conductive material is then selectively applied to the extruded substrate material and the Z-directed component is formed from the extruded substrate material.
Abstract translation: 根据一个示例实施例的用于制造用于插入到印刷电路板的安装孔中的Z定向部件的方法包括根据Z指向部件的形状挤出基底材料。 然后将导电材料选择性地施加到挤出的基底材料上，并且由挤出的基底材料形成Z指向的部件。
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20.发明申请公开(公告)号：US20140151104A1
公开(公告)日：2014-06-05
申请号：US14090469
申请日：2013-11-26
Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
Inventor： Yul Kyo CHUNG , DOO HWAN LEE , SEUNG EUN LEE , YEE NA SHIN
CPC classification number: H05K1/186 , H05K3/403 , H05K3/4602 , H05K2201/09645 , H05K2203/0228 , H05K2203/0242 , Y10T29/49139
Abstract: The present invention relates to an electronic component embedded substrate including: a cavity formed in at least one insulating layer provided inside the electronic component embedded substrate; an electronic component having at least a portion inserted in the cavity; and a cavity plating portion formed on a surface of the cavity opposite to at least one surface of the electronic component, and can improve electrical connectivity between an external electrode and a via even when the size of the external electrode of the electronic component is reduced than before.
Abstract translation: 电子部件嵌入式基板技术领域本发明涉及一种电子部件嵌入式基板，包括：形成在设置在电子部件嵌入基板的内部的至少一个绝缘层内的空腔; 电子部件，其具有插入到所述空腔中的至少一部分; 以及形成在与所述电子部件的至少一个表面相对的所述空腔的表面上的空腔镀敷部，并且即使当所述电子部件的外部电极的尺寸比所述电子部件的尺寸小的情况下，也能够提高外部电极和通孔之间的电连接性 之前。
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