公开(公告)号：US20020042823A1

公开(公告)日：2002-04-11

申请号：US09929997

申请日：2001-08-15

Inventor： Jason DeBettencourt ,  Marco Lara ,  Stanley Yamane ,  Freeland Abbott

IPC: G06F015/16

CPC classification number: G06F11/0709 ,  G06F11/0793 ,  G06F11/3419 ,  G06F11/3433 ,  G06F11/3495 ,  G06F17/3089 ,  G06F2201/81 ,  G06F2201/86 ,  G06F2201/87 ,  G06F2201/875 ,  G06F2201/88 ,  H04L41/046 ,  H04L41/0654 ,  H04L41/0896 ,  H04L41/5083 ,  H04L67/02 ,  H04L67/1002 ,  H04L67/1008 ,  H04L67/1012 ,  H04L67/1019 ,  H04L67/1029 ,  H04L67/1031 ,  H04L67/1034 ,  H04L67/1095 ,  H04L67/142 ,  Y10S707/99944 ,  Y10S707/99945

Abstract: A system for serving web pages manages a plurality of web servers. The system provides an operator with features and tools to coordinate the operation of the multiple web servers. The system can manage traffic by directing web page requests to available web servers and balancing the web page request service load among the multiple servers. The system can collect data on web page requests and web server responses to those web page requests, and provide reporting of the data as well as automatic and manual analysis tools. The system can monitor for specific events, and can act automatically upon the occurrence of such events. The events can include predictions or thresholds that indicate impending system crises. The system can include crisis management capability to provide automatic error recovery, and to guide a system operator through the possible actions that can be taken to recover from events such as component failure or network environment problems. The system can present current information about the system operation to a system operator. The system can manage content replication.

Abstract translation: 用于服务网页的系统管理多个web服务器。 该系统为操作员提供功能和工具来协调多个Web服务器的操作。 系统可以通过将网页请求定向到可用的Web服务器并在多个服务器之间平衡网页请求服务负载来管理流量。 系统可以收集关于网页请求和Web服务器响应这些网页请求的数据，并提供数据报告以及自动和手动分析工具。 系统可以监视特定的事件，并可以在发生这种事件时自动执行。 这些事件可以包括指示即将发生的系统危机的预测或阈值。 该系统可以包括危机管理功能，以提供自动错误恢复，并引导系统操作员通过可能采取的行动，从组件故障或网络环境问题等事件中恢复。 系统可以向系统操作员呈现关于系统操作的当前信息。 系统可以管理内容复制。

公开(公告)号：US06360337B1

公开(公告)日：2002-03-19

申请号：US09238246

申请日：1999-01-27

Applicant: Robert C. Zak ,  Hien H. Nguyen ,  Monica C. Wong-Chan

Inventor： Robert C. Zak ,  Hien H. Nguyen ,  Monica C. Wong-Chan

IPC: G06F1100

CPC classification number: G06F11/3409 ,  G06F11/3466 ,  G06F2201/86 ,  G06F2201/87 ,  G06F2201/88 ,  G06F2201/885

Abstract: A performance counter to monitor a plurality of events that may occur in a component within a computer system during a monitoring period or testing period. The monitoring results, which are provided upon completion of the performance testing, may be used to provide histogram representations of the component performance. In one embodiment, the performance counter comprises a first storage, a second storage, programmable control logic, and a counting mechanism. The first storage is configured to store information indicative of a plurality of events to be monitored and the monitoring period for each event. The second storage is configured to store counting results obtained during the testing period. A counting mechanism, which is coupled to the second storage, is configured to monitor the occurrence of the events in the component under test. The counting mechanism is coupled to the control logic and the control logic is coupled to the first storage.

Abstract translation: 一种性能计数器，用于在监视期间或测试期间监视可能在计算机系统内的组件中发生的多个事件。 在性能测试完成后提供的监视结果可用于提供组件性能的直方图表示。 在一个实施例中，性能计数器包括第一存储器，第二存储器，可编程控制逻辑器件和计数机构。 第一存储器被配置为存储指示要监视的多个事件的信息和每个事件的监视周期。 第二存储器被配置为存储在测试期间获得的计数结果。 耦合到第二存储器的计数机构被配置为监视被测组件中的事件的发生。 计数机制耦合到控制逻辑，并且控制逻辑耦合到第一存储器。

公开(公告)号：US06341260B2

公开(公告)日：2002-01-22

申请号：US09761904

申请日：2001-01-17

Applicant: Paul F. Klein ,  Raymond P. Ammerman, III

Inventor： Paul F. Klein ,  Raymond P. Ammerman, III

IPC: G04F1000

CPC classification number: G06F11/3419 ,  G06F11/3438 ,  G06F2201/87

Abstract: A method, apparatus, and article of manufacture for measuring end-to-end response time for a transaction performed by a computer is disclosed. The method comprises the steps of monitoring a start queue and an end queue in a computer, assigning a start time when a first message is received at the start queue, assigning a stop time when a second message, sent in response to the first message, is received at the end queue, and subtracting the start time from the stop time to calculate an end-to-end response time.

Abstract translation: 公开了一种用于测量由计算机进行的交易的端到端响应时间的方法，装置和制品。 该方法包括以下步骤：监视计算机中的起始队列和结束队列，分配在起始队列处接收到第一消息的开始时间;当响应于第一消息发送的第二消息分配停止时间时， 在结束队列中被接收，并且从停止时间减去开始时间以计算端到端响应时间。

公开(公告)号：US06336170B1

公开(公告)日：2002-01-01

申请号：US09170898

申请日：1998-10-13

Applicant: Mark E. Dean ,  James Michael Magee ,  Ronald Lynn Rockhold ,  Guy G. Sotomayor, Jr. ,  James Van Fleet

Inventor： Mark E. Dean ,  James Michael Magee ,  Ronald Lynn Rockhold ,  Guy G. Sotomayor, Jr. ,  James Van Fleet

IPC: G06F1200

CPC classification number: G06F11/3409 ,  G06F9/5016 ,  G06F2201/87 ,  G06F2201/88

Abstract: A method and system in a distributed shared-memory data processing system are disclosed having a single operating system being executed simultaneously by a plurality of processors included within a plurality of coupled processing nodes for determining a utilization of each memory location included within a shared-memory included within each of the plurality of nodes by each of the plurality of nodes. The operating system processes a designated application utilizing the plurality of nodes. During the processing, for each of the plurality of nodes, a determination is made of a quantity of times each memory location included within a shared-memory included within each of the plurality of nodes is accessed by each of the plurality of nodes.

Abstract translation: 公开了一种分布式共享存储器数据处理系统中的方法和系统，其具有由包括在多个耦合处理节点内的多个处理器同时执行的单个操作系统，用于确定包括在共享存储器内的每个存储器位置的使用 由所述多个节点中的每个节点包括在所述多个节点的每一个节点内。 操作系统使用多个节点处理指定的应用程序。 在处理期间，对于多个节点中的每一个节点，确定包括在多个节点中的每个节点内的共享存储器内的每个存储器位置的每个节点访问的次数。

公开(公告)号：US06256620B1

公开(公告)日：2001-07-03

申请号：US09008523

申请日：1998-01-16

Applicant: Janardhanan Jawahar ,  Venkatachari Dilip

Inventor： Janardhanan Jawahar ,  Venkatachari Dilip

IPC: G06F1730

CPC classification number: G06F17/30873 ,  G06F11/323 ,  G06F11/3495 ,  G06F2201/87 ,  G06F2201/875 ,  Y10S707/99932 ,  Y10S707/99945

Abstract: A system is described for monitoring information access. The system provides an access monitoring application to an information accessing system. The access monitoring application monitors information accessed by the information accessing system. Data is received from the information accessing system which identifies the information accessed by the information accessing system. The information accessing system may use a web browser application to access information stored in web pages and the access monitoring application may monitor web pages accessed by the web browser application. The system terminates the monitoring of information access if the information accessing system stops accessing information.

Abstract translation: 描述了一种用于监视信息访问的系统。 该系统向信息访问系统提供访问监控应用程序。 访问监控应用程序监视信息访问系统访问的信息。 从信息访问系统接收数据，其识别信息访问系统访问的信息。 信息访问系统可以使用Web浏览器应用来访问存储在网页中的信息，并且访问监视应用可以监视由web浏览器应用访问的网页。 如果信息访问系统停止访问信息，系统终止对信息访问的监视。

公开(公告)号：US06253286B1

公开(公告)日：2001-06-26

申请号：US09368755

申请日：1999-08-05

Applicant: Ravi Kumar Arimilli ,  John Steve Dodson ,  Guy Lynn Guthrie

Inventor： Ravi Kumar Arimilli ,  John Steve Dodson ,  Guy Lynn Guthrie

IPC: G06F1314

CPC classification number: G06F9/30043 ,  G06F9/3004 ,  G06F9/3834 ,  G06F11/3409 ,  G06F12/0811 ,  G06F12/0837 ,  G06F2201/86 ,  G06F2201/87 ,  G06F2201/88 ,  G06F2201/885

Abstract: An apparatus for adjusting a STORE instruction having memory hierarchy control bits is disclosed. A multiprocessor data processing system includes a multi-level memory hierarchy. The apparatus for adjusting control bits within an instruction to be utilized within the multi-level memory hierarchy comprises a performance monitor and a bit adjuster. The memory hierarchy control bits indicates a memory level within the multi-level memory hierarchy to which an updating operation should be applied. In response to the outputs from the performance monitor, the bit adjuster alters at least one of the memory hierarchy control bits within the instruction in order to achieve optimal performance for the updating operation.

Abstract translation: 公开了一种用于调整具有存储器层级控制位的STORE指令的装置。 多处理器数据处理系统包括多级存储器层次结构。 用于调整要在多级存储器层级内使用的指令内的控制位的装置包括性能监视器和位调节器。 存储器层级控制位指示应该应用更新操作的多级存储器层级中的存储器级别。 响应于性能监视器的输出，位调整器改变指令内的存储器层级控制位中的至少一个，以便实现更新操作的最佳性能。

公开(公告)号：US20010002463A1

公开(公告)日：2001-05-31

申请号：US09761904

申请日：2001-01-17

Inventor： Paul F. Klein ,  Raymond P. Ammerman III

IPC: G04F001/00

CPC classification number: G06F11/3419 ,  G06F11/3438 ,  G06F2201/87

Abstract: An end-to-end response time measurement method monitors the performance of a computer program by measuring the time between related messages that traverse inbound and outbound message queues.

公开(公告)号：US06237059B1

公开(公告)日：2001-05-22

申请号：US08979398

申请日：1997-11-26

Applicant: Jeffrey A. Dean ,  Carl A. Waldspurger

Inventor： Jeffrey A. Dean ,  Carl A. Waldspurger

IPC: G06F1200

CPC classification number: G06F9/4881 ,  G06F11/3452 ,  G06F11/3466 ,  G06F11/3471 ,  G06F12/08 ,  G06F2201/86 ,  G06F2201/87 ,  G06F2201/88 ,  G06F2201/885

Abstract: A method analyzes memory transaction processed by memories of a computer system. The method selects a set of addresses of the memories. State information from a plurality of consecutive predetermined memory transactions to the selected addresses are recorded while the selected transactions are processed by the memories. The selecting and the recording steps are repeated until a termination condition is reached. Then, the recorded state information is statistically analyzed to estimate statistics of properties of the memory interactions among contexts in the computer system.

Abstract translation: 一种分析由计算机系统的存储器处理的存储器事务的方法。 该方法选择存储器的一组地址。 在所选择的事务被存储器处理的同时记录从多个连续的预定存储器事务到所选地址的状态信息。 重复选择和记录步骤，直到达到终止条件。 然后，记录的状态信息被统计分析以估计计算机系统中的上下文之间的存储器交互的属性的统计。

公开(公告)号：US06195731B1

公开(公告)日：2001-02-27

申请号：US09083154

申请日：1998-05-22

Applicant: Thierry Bordaz ,  Jean-Dominique Sorace

Inventor： Thierry Bordaz ,  Jean-Dominique Sorace

IPC: G06F1200

CPC classification number: G06F11/348 ,  G06F12/0813 ,  G06F2201/87 ,  G06F2201/88 ,  G06F2201/885 ,  G06F2212/2542

Abstract: A machine with non-uniform memory access and cache coherency is constituted by a plurality of modules (10, 20, 40, 60), each module comprising a unit (6, 26, 46, 66), the unit (6) comprising at least one table (8) for managing local accesses to a memory part (5′) local to the module (10) and one table (9) for managing accesses to a memory part (25′, 45′, 65′) remote from the module (10), by means of a system bus (7). The machine comprises: a counter (81) of hits in the local memory part (5′) without a transaction with a remote module; a counter (82) of misses in the local memory part (5′) accompanied by at least one transaction with a remote module; a counter (91) of hits in the remote memory part (25′, 25′, 65′) without a transaction with a remote module; a counter (92) of misses in the remote memory part (25′, 45′, 65′) accompanied by at least one transaction with a remote module.

Abstract translation: 具有不均匀存储器访问和高速缓存一致性的机器由多个模块（10,20,40,60）构成，每个模块包括单元（6,26,46,66），所述单元（6）包括： 用于管理对模块（10）本地的存储器部分（5'）的本地访问的最少一个表格（8）和用于管理对远程访问的存储器部分（25'，45'，65'）的访问的表格（9） 所述模块（10）借助于系统总线（7）。 该机器包括：与本地存储器部分（5'）中的命中计数器（81）而没有与远程模块进行交易;在本地存储器部分（5'）中丢失的计数器（82），伴随着至少一个事务 远程模块;远程存储器部分（25'，25'，65'）中的命中计数器（91），而不与远程模块进行交易;远程存储器部分（25'）中的错过的计数器（92） ，45'，65'），伴随着与远程模块的至少一个交易。

公开(公告)号：US06178449B1

公开(公告)日：2001-01-23

申请号：US08979224

申请日：1997-11-26

Applicant: Ron Frank Forman ,  John M. Pechacek ,  Walter H. Schwane

Inventor： Ron Frank Forman ,  John M. Pechacek ,  Walter H. Schwane

IPC: G06F15173

CPC classification number: G06F11/3495 ,  G06F11/3419 ,  G06F2201/87 ,  G06F2201/875 ,  H04L41/0213 ,  H04L41/0233 ,  H04L41/046 ,  H04L43/00 ,  H04L67/02 ,  H04L67/42 ,  H04L69/329

Abstract: A transaction time measurement mechanism has a transaction time manager running on a server computer system, a transaction time agent running on a client computer system that is coupled to the server computer system via a network, and a simple protocol for allowing them to directly and efficiently communicate. The transaction time agent is configured according to configuration data stored in a configuration table in a transaction time database, and stores transaction time data in a statistics table according to this configuration. The data in the statistics table is indexed to allow retrieving only the transaction time data of interest. The simple communication protocol supports multiple transaction time managers in a network computing environment that may all communicate with a single client.

Abstract translation: 事务时间测量机制具有在服务器计算机系统上运行的事务时间管理器，在通过网络耦合到服务器计算机系统的客户端计算机系统上运行的事务时间代理以及用于允许它们直接和有效地使用的简单协议 通信。 交易时间代理根据存储在交易时间数据库中的配置表中的配置数据来配置，并且根据该配置将交易时间数据存储在统计表中。 统计表中的数据被索引，以便仅检索感兴趣的事务时间数据。 简单的通信协议支持可以与单个客户端通信的网络计算环境中的多个事务时间管理器。