公开(公告)号：US20030008182A1

公开(公告)日：2003-01-09

申请号：US10182198

申请日：2002-07-26

Inventor： Yoshifumi Saitoh ,  Hiromichi Kawakami

IPC: C04B035/64

CPC classification number: C04B35/6264 ,  B28B11/243 ,  B28B17/0018 ,  B32B18/00 ,  B32B37/0046 ,  B32B2311/12 ,  C04B35/638 ,  C04B2235/3206 ,  C04B2235/3208 ,  C04B2235/3217 ,  C04B2235/3244 ,  C04B2235/3409 ,  C04B2235/3418 ,  C04B2235/3463 ,  C04B2235/3481 ,  C04B2235/365 ,  C04B2235/5445 ,  C04B2235/6025 ,  C04B2237/407 ,  C04B2237/56 ,  C04B2237/562 ,  C04B2237/565 ,  C04B2237/568 ,  C04B2237/64 ,  C04B2237/66 ,  C04B2237/702 ,  C04B2237/704 ,  H01L21/4807 ,  H01L21/481 ,  H01L21/4857 ,  H01L23/15 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/0306 ,  H05K3/0052 ,  H05K3/4611 ,  H05K3/4629 ,  H05K2201/09036 ,  H05K2201/0909 ,  H05K2203/308 ,  Y02P40/63 ,  H01L2924/00

Abstract: A method of producing a ceramic multilayer substrate comprising the steps of: as a first step, producing a green composite laminate 11 containing first and second shrink-suppressing layers formed on one main surface 13 and the other main surface 14 of a green multilayer mother substrate 12 comprising a plurality of ceramic green layers 17 containing ceramic powder, the first and second shrink-suppressing layers containing a sintering-difficult powder substantially incapable of being sintered under the sintering conditions for the ceramic powder; as a second step, forming first grooves 16 extending from the first shrink-suppressing layer 13 side so as to pass through the first shrink-suppressing layer 13 and reach a part of the multilayer mother substrate 12; as a third step, firing the composite laminate 11; as a fourth step, removing the first and second shrink-suppressing layers 13 and 14 and taking out the sintered multilayer mother substrate 11; and as a fourth step, dividing the multilayer mother substrate 12 along the groovres 16, and taking out a plurality of the ceramic multilayer substrates. Thereby, the shrink in the plan direction at firing can be suppressed. Thus, a ceramic multilayer substrate having a high dimensional accuracy and a high reliability can be produced with a high production efficiency.

Abstract translation: 一种制造陶瓷多层基板的方法，包括以下步骤：作为第一步骤，制备包含形成在一个主表面13和绿色多层母基板的另一个主表面14上的第一和第二收缩抑制层的生坯复合层压体11 12包括含有陶瓷粉末的多个陶瓷生坯层17，第一和第二收缩抑制层含有烧结难熔粉末，其基本上不能在陶瓷粉末的烧结条件下烧结; 作为第二步骤，形成从第一收缩抑制层13侧延伸出的第一槽16，以通过第一收缩抑制层13并到达多层母体基板12的一部分; 作为第三步骤，烧制复合层压体11; 作为第四步骤，除去第一和第二收缩抑制层13和14并取出烧结的多层母体基板11; 并且作为第四步骤，沿着树脂16分离多层母体基板12，并取出多个陶瓷多层基板。 由此，能够抑制烧成时的平面方向的收缩。 因此，可以以高生产效率制造具有高尺寸精度和高可靠性的陶瓷多层基板。

公开(公告)号：US20020078560A1

公开(公告)日：2002-06-27

申请号：US09746774

申请日：2000-12-21

Applicant: Xerox Corporation

Inventor： Harry J. M. Reijnders

IPC: H05K003/10 ,  H05K003/02

CPC classification number: H05K1/148 ,  H05K3/0052 ,  H05K2201/09036 ,  H05K2201/0909 ,  H05K2201/10287 ,  H05K2203/0195 ,  H05K2203/302 ,  Y10T29/49155

Abstract: Printed wiring boards are often joined on a motherboard in order to optimize use of cabinet space. The process of the present invention enables more efficient manufacture and assembly of adjoining printed wiring boards. The steps of the inventive process comprise forming multiple circuits upon a common substrate before the common substrate is separated into separate boards; making interconnections between the separate boards, preferably in situ and before the boards are separated; and separating the common substrate into a plurality of separate interconnected boards. Using the inventive process, interconnections between boards can be fully tested on a single substrate and inventory and handling processes relating to joining of separate boards can be simplified or eliminated.

Abstract translation: 印刷电路板通常连接在主板上，以优化机柜空间的使用。 本发明的方法能够更有效地制造和组装相邻的印刷线路板。 本发明方法的步骤包括在公共衬底分离成单独的板之前在公共衬底上形成多个电路; 在单独的板之间进行互连，优选在原位和板分离之前; 以及将所述公共基板分离成多个单独的互连板。 使用本发明的工艺，可以在单个基板上完全测试板之间的互连，并且可以简化或消除与分离板的接合相关的库存和处理过程。

公开(公告)号：US20010008043A1

公开(公告)日：2001-07-19

申请号：US09788808

申请日：2001-02-20

Inventor： Yukiko Daido ,  Yoshihisa Hatta

IPC: H05K003/30

CPC classification number: H05K1/0271 ,  H05K3/0052 ,  H05K3/0097 ,  H05K3/34 ,  H05K3/3405 ,  H05K2201/09063 ,  H05K2201/0909 ,  H05K2201/10446 ,  Y10T29/4913 ,  Y10T29/49133 ,  Y10T29/49144 ,  Y10T29/49165

Abstract: A method of making a circuit board (10) on which surface electronic components (15) are mounted during the method using a solder reflow process. The board comprises a circuit portion (12), a surrounding circumferential portion (13) and at least one elongated opening (14) formed in the surrounding circumferential portion substantially parallel to the direction that the board travels during the reflow direction (16), thereby preventing electronic component soldering failures that may occur as a result of the deflection of the circuit board during the reflow process.

Abstract translation: 一种制造电路板（10）的方法，在该方法期间使用焊料回流工艺安装表面电子部件（15）。 板包括电路部分（12），周围圆周部分（13）和形成在围绕圆周部分的至少一个细长开口（14），其基本上平行于板在回流方向（16）处行进的方向，从而 防止在回流过程中由于电路板的偏转而可能发生的电子部件焊接故障。

公开(公告)号：US06225573B1

公开(公告)日：2001-05-01

申请号：US09180978

申请日：1998-11-18

Applicant: Satoshi Nakamura

Inventor： Satoshi Nakamura

IPC: H01R1204

CPC classification number: H05K3/3405 ,  H01R12/52 ,  H05K3/0052 ,  H05K3/0097 ,  H05K3/305 ,  H05K3/341 ,  H05K3/3421 ,  H05K3/3452 ,  H05K3/3484 ,  H05K2201/083 ,  H05K2201/09036 ,  H05K2201/0909 ,  H05K2201/09909 ,  H05K2201/1028 ,  H05K2201/1034 ,  H05K2203/0545 ,  H05K2203/104 ,  H05K2203/167 ,  Y02P70/613 ,  Y10T29/49147 ,  Y10T29/49149

Abstract: There are provided a coating step for coating solder paste (3) onto the circuit board (1), a superimposing step for superimposing a connecting end (4a) of a terminal (4) also having a non-connecting end (4b) on the regions coated with solder paste (3), and a heating step for heating and melting the solder paste (3) in order to solder the connecting end (4a) onto the circuit board (1). A further step for coating adhesive material (6) onto the circuit board (1) is provided, and in the aforementioned superimposing step, the connecting end (4a) is brought into contact with the regions coated with the adhesive material (6). In the aforementioned heating step, the solder paste (3) is heated and caused to melt whilst the connecting end (4a) is in a bonded state with respect to the circuit board (1) by means of the adhesive material (6).

Abstract translation: 提供了一种用于将焊膏（3）涂覆到电路板（1）上的涂覆步骤，用于将也具有非连接端（4b）的端子（4）的连接端（4a）重叠在其上的叠加步骤 涂覆有焊膏（3）的区域，以及用于加热和熔化焊膏（3）的加热步骤，以将连接端（4a）焊接到电路板（1）上。 提供了将粘合剂材料（6）涂覆到电路板（1）上的另一步骤，并且在上述重叠步骤中，连接端（4a）与涂覆有粘合剂材料（6）的区域接触。 在上述加热步骤中，焊膏（3）被加热并熔化，同时连接端（4a）通过粘合材料（6）相对于电路板（1）处于接合状态。

公开(公告)号：US06218628B1

公开(公告)日：2001-04-17

申请号：US08581625

申请日：1996-01-18

Applicant: Walter Schmidt ,  Marco Martinelli

Inventor： Walter Schmidt ,  Marco Martinelli

IPC: H05K304

CPC classification number: H05K3/403 ,  H01L21/4857 ,  H01L23/5387 ,  H01L2924/0002 ,  H05K1/0218 ,  H05K1/0393 ,  H05K1/118 ,  H05K3/0041 ,  H05K3/0052 ,  H05K3/3442 ,  H05K3/363 ,  H05K3/427 ,  H05K3/428 ,  H05K3/4652 ,  H05K2201/09063 ,  H05K2201/09081 ,  H05K2201/0909 ,  H05K2201/09172 ,  H05K2203/0554 ,  H05K2203/0557 ,  Y10T29/49121 ,  Y10T29/49171 ,  Y10T428/24917 ,  H01L2924/00

Abstract: A method for the manufacture of printed circuit boards, foil circuit boards and semifinished products for printed and foil circuit boards formed from preliminary products with electrically conductive coatings (7, 8) structurable to conductor patterns and structurable substrates (4), for the formation of connectors (V), contours (K) and conductor patterns (L), the connectors (V), contours (K) and conductor patterns (L) being structured simultaneously or in the same method steps from the preliminary products, and the connectors (V) and contours (K) are part of the structured preliminary product substrate, the connectors (V) being brought for electrical or mechanical connection into a position in which they are connectable and the finished conductor patterns (L) can be separated at contours (K).

Abstract translation: 一种用于制造印刷电路板，箔电路板和用于印刷和箔电路板的半成品的方法，其由具有可导电图案和可结构化基板（4）的可导电涂层（7,8））的初步产品形成，用于形成 连接器（V），轮廓（K）和导体图案（L），连接器（V），轮廓（K）和导体图案（L）同时或以与初步产品相同的方法步骤构成， V）和轮廓（K）是结构化初步产品基板的一部分，连接器（V）用于电气或机械连接到可连接的位置，并且完成的导体图案（L）可以在轮廓处分开 K）。

公开(公告)号：US6113999A

公开(公告)日：2000-09-05

申请号：US397875

申请日：1999-09-17

Applicant: Kotaro Takigami

Inventor： Kotaro Takigami

IPC: H05K1/02 ,  B32B3/10 ,  B32B37/12 ,  H05K3/00 ,  H05K3/46

CPC classification number: B32B3/10 ,  B32B38/0004 ,  H05K3/0052 ,  B32B2038/047 ,  B32B2457/08 ,  B32B37/12 ,  H05K2201/09036 ,  H05K2201/09063 ,  H05K2201/0909 ,  H05K2201/09827 ,  H05K3/0097 ,  H05K3/46 ,  H05K3/4644 ,  Y10T156/1056 ,  Y10T156/1057 ,  Y10T156/1082 ,  Y10T428/15 ,  Y10T428/24314 ,  Y10T428/24322 ,  Y10T428/24612

Abstract: A multilayered substrate divisible into a plurality of parts at predetermined positions of division is configured such that intermittently formed perforation-like holes or slit-like holes are present at the positions of division of a core layer. Further, V-cut V-grooves are present at the positions of division of surface layers. The multilayered substrate, divisible at predetermined positions of division, is also configured such that first intermittently formed holes (perforation-like holes, slit-like holes, or widely spaced holes) are present at the positions of division of the core layer. Further, second intermittently formed holes (perforation-like holes, or slit-like holes) are present at the positions of division of the surface layers so as to pass through the multilayered substrate. At the positions of division of the core layer, each of the second holes is located between the adjacent first holes, whereby the first holes and the second holes are continuous with each other. Methods for production of these multilayered substrates are also disclosed.

Abstract translation: 在分割的预定位置处可分割成多个部分的多层基板被构造为使得在芯层的分割位置处存在间歇形成的穿孔状孔或狭缝状孔。 此外，在划分表面层的位置处存在V形V形凹槽。 在预定的分割位置处可分割的多层基板也被构造为使得在芯层的分割位置处存在第一间断地形成的孔（穿孔状的孔，狭缝状的孔或宽间隔开的孔）。 此外，在划分表面层的位置处存在第二间歇形成的孔（穿孔状的孔或狭缝状的孔），以通过多层基板。 在芯层的分割位置，每个第二孔位于相邻的第一孔之间，由此第一孔和第二孔彼此连续。 还公开了这些多层基板的制造方法。

公开(公告)号：US6113835A

公开(公告)日：2000-09-05

申请号：US28454

申请日：1998-02-24

Applicant: Shigeya Kato ,  Yasutaka Kamiya ,  Takashi Ogata ,  Takashi Hiraiwa

Inventor： Shigeya Kato ,  Yasutaka Kamiya ,  Takashi Ogata ,  Takashi Hiraiwa

IPC: B23K26/00 ,  B23K26/06 ,  B23K26/18 ,  B23K26/40 ,  B29C35/08 ,  B29C59/00 ,  B29C59/16 ,  H05K1/00 ,  H05K3/00

CPC classification number: H05K3/0032 ,  B23K26/18 ,  B23K26/364 ,  B23K26/402 ,  B29C59/007 ,  B29C59/16 ,  B23K2203/42 ,  B29C2035/0838 ,  H05K1/0393 ,  H05K2201/0129 ,  H05K2201/09036 ,  H05K2201/09063 ,  H05K2201/0909 ,  H05K2203/0165 ,  H05K2203/1383 ,  H05K3/0052 ,  H05K3/0097

Abstract: A method of forming a separation groove and a ditch for cutting a thermoplastic resin sheet by a laser beam is performed as follows. A heat-resistant layer made of thermosetting resin is printed on the rear surface of the resin sheet along the line of the ditch to be formed by the laser beam. A laser beam is radiated on the front surface of the resin sheet and scanned along the line of the ditch and the separation groove. The laser beam melts and evaporates resin and forms the ditch and the separation groove. Since the rear end of the ditch is covered by the heat-resistant layer, the resin sheet is not completely separated along the ditch line, while it is separated along the separation groove line. At the final stage, the resin sheet is cut along the ditch line. A flexible circuit sheet for making electrical connection can be easily and cost effectively processed in this laser beam process.

Abstract translation: 通过激光束形成用于切割热塑性树脂片的分离槽和沟槽的方法如下进行。 沿着由激光束形成的沟槽的线，在树脂片的后表面上印刷由热固性树脂制成的耐热层。 激光束照射在树脂片的前表面上，沿着沟槽和分隔槽的线扫描。 激光束熔化并蒸发树脂，形成沟槽和分隔槽。 由于沟槽的后端由耐热层覆盖，所以树脂片沿着沟槽线沿着分离槽线分离，并不完全分离。 在最后阶段，沿着沟线切割树脂片。 用于进行电连接的柔性电路板可以在该激光束工艺中容易且经济地处理。

公开(公告)号：US6053084A

公开(公告)日：2000-04-25

申请号：US192157

申请日：1998-11-13

Applicant: Ivan Pawlenko

Inventor： Ivan Pawlenko

IPC: H05K3/00 ,  H05K3/02

CPC classification number: H05K3/0052 ,  H05K2201/09063 ,  H05K2201/0909 ,  H05K2203/0228 ,  Y10T29/49155 ,  Y10T83/0448 ,  Y10T83/2192 ,  Y10T83/531 ,  Y10T83/6539 ,  Y10T83/6576 ,  Y10T83/6577 ,  Y10T83/6584 ,  Y10T83/6606 ,  Y10T83/741 ,  Y10T83/745 ,  Y10T83/764 ,  Y10T83/7797 ,  Y10T83/7843 ,  Y10T83/7859 ,  Y10T83/9403

Abstract: This invention relates to a system and method for cutting circuit board panels utilizing an in-line cutting mechanism. As the panel is transported into the cutting mechanism, adjustable rails are moved into position to properly guide the panel into the cutting head. The actual cutting operation is performed by transporting the panel between an upper cutting disk blade and a lower cutting disk blade. The distance between these two blades is adjustable and permits precision cutting of the panel with minimal stress to the circuit board and its components.

Abstract translation: 本发明涉及一种使用直列切割机构切割电路板面板的系统和方法。 当面板被输送到切割机构中时，可调节的轨道被移动到适当位置以将面板适当地引导到切割头中。 通过在上切割盘片和下切割盘片之间传送面板来执行实际的切割操作。 这两个刀片之间的距离是可调节的，并允许对电路板及其部件施加最小应力的面板的精确切割。

公开(公告)号：US5897334A

公开(公告)日：1999-04-27

申请号：US951062

申请日：1997-10-15

Applicant: Sun Ho Ha ,  Young Wook Heo ,  Byung Joon Han

Inventor： Sun Ho Ha ,  Young Wook Heo ,  Byung Joon Han

IPC: H01L23/28 ,  H01L21/50 ,  H01L21/66 ,  H01L23/12 ,  H01L23/498 ,  H05K1/00 ,  H05K3/00 ,  H05K3/22 ,  H01L21/44

CPC classification number: H01L22/22 ,  H01L23/4985 ,  H01L24/97 ,  H05K3/0097 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/0393 ,  H05K2201/09063 ,  H05K2201/0909 ,  H05K2203/1545 ,  H05K3/0052 ,  H05K3/225

Abstract: A method for reproducing a PCB strip for semiconductor packages, wherein a poor quality PCB unit included in the PCB strip is replaced with a normal quality one, thereby achieving a reduction in the amount of package materials used and an improvement in the process efficiency. The invention also provides a method for fabricating semiconductor packages using the PCB strip reproduction method. A desired portion of a poor quality PCB unit included in a PCB strip is cut out in such a manner that a cutting opening having a peripheral edge extending along the singulation line of the poor quality PCB unit or along a region defined between the singulation line and anti-bending slots of the poor quality PCB unit. In the cutting opening, a separate good quality PCB unit member having the same shape and size as the cutting opening is then fitted. Thus, it is possible to simply and efficiently replace PCB units determined to be of poor quality with separate good quality PCB unit members, respectively.

Abstract translation: 一种用于再现用于半导体封装的PCB板的方法，其中包括在PCB板中的劣质PCB单元被正常的质量替换，从而实现所使用的封装材料的量的减少和工艺效率的提高。 本发明还提供了一种使用PCB条带再现方法制造半导体封装的方法。 包含在PCB带中的劣质PCB单元的期望部分以这样的方式被切出：具有周边边缘的切割开口沿着劣质PCB单元的单线延伸，或者沿着限定在单线线和 抗弯槽的质量差的PCB单元。 在切割开口中，然后安装具有与切割开口相同的形状和尺寸的单独的优质PCB单元构件。 因此，可以分别用单独的优质PCB单元构件简单有效地替代被确定为质量差的PCB单元。

公开(公告)号：US5835781A

公开(公告)日：1998-11-10

申请号：US376540

申请日：1995-01-20

Applicant: Kerry Van de Steeg ,  Gerald S. Pepera ,  Gene S. Laurich ,  James E. Schey

Inventor： Kerry Van de Steeg ,  Gerald S. Pepera ,  Gene S. Laurich ,  James E. Schey

IPC: G06F21/00 ,  G07F7/10 ,  H05K1/02 ,  G06F15/00

CPC classification number: G07F7/1008 ,  G06F21/86 ,  G06Q20/341 ,  G07F7/082 ,  H05K1/0275 ,  H05K2201/0909 ,  H05K2201/09127 ,  H05K2201/10151 ,  H05K2203/175

Abstract: A structural key is checked under program control to control the mode of operation for a processor-based electronic circuit board. A break-away key portion of the circuit board is connected to the main portion along a boundary of frangible links with circuit paths traversing the boundary and carrying logic signals. The presence or absence of the break-away portion is sensed by sensing the bit pattern at an I/O address. If the absence of the break-away portion is sensed, the function of a user-commanded motion block is tested and processor operation is limited to executing functions for the mode corresponding to the absence of the break-away portion.

Abstract translation: 在程序控制下检查结构键以控制基于处理器的电子电路板的操作模式。 电路板的断开键部分沿着具有穿过边界的电路路径和承载逻辑信号的易断链路的边界连接到主要部分。 通过感测I / O地址处的位模式来感测到分离部分的存在或不存在。 如果没有感测到分离部分，则测试用户命令的运动块的功能，并且将处理器操作限于对应于不存在分离部分的模式的执行功能。