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241.发明授权公开(公告)号：US08058951B2
公开(公告)日：2011-11-15
申请号：US11997178
申请日：2006-09-22
Applicant: Kenichi Yamamoto , Daido Komyoji , Keizaburo Kuramasu
Inventor： Kenichi Yamamoto , Daido Komyoji , Keizaburo Kuramasu
IPC: H03H7/00
CPC classification number: H05K1/16 , H01L23/66 , H01L27/016 , H01L2924/0002 , H03H7/0115 , H03H7/175 , H05K1/162 , H05K1/165 , H05K3/4614 , H05K2201/0317 , H05K2201/086 , H05K2201/09763 , H05K2203/1189 , Y10T29/49155 , H01L2924/00
Abstract: A configuration includes a first sheet substrate, on which a first thin film electronic component is formed on at least one main face, and an external connection terminal for connecting to an external circuit is formed one main face or the other face; a second sheet substrate, on which a second thin film electronic component is formed on at least one face; an insulator connection resin layer for fixing the first sheet substrate and the second sheet substrate opposing the first thin film electronic component against the second thin film electronic component; and an interlayer connection conductor for electrically connecting electrode terminals, which have been set in advance, of the first thin film electronic component and the second thin film electronic component.
Abstract translation: 一种构造包括：第一薄片基板，其上形成有至少一个主面上的第一薄膜电子部件，并且用于连接到外部电路的外部连接端子形成为一个主面或另一个面; 第二片基板，在至少一个面上形成有第二薄膜电子部件; 绝缘体连接树脂层，用于将第一薄片基板和与第一薄膜电子部件相对的第二薄片基板固定在第二薄膜电子部件上; 以及用于电连接第一薄膜电子部件和第二薄膜电子部件的预先设定的电极端子的层间连接导体。
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公开(公告)号：US07918019B2
公开(公告)日：2011-04-05
申请号：US12351767
申请日：2009-01-09
Applicant: Shih Chang Chang , John Z. Zhong , Lili Huang , Seung Jae Hong , Lynn Youngs
Inventor： Shih Chang Chang , John Z. Zhong , Lili Huang , Seung Jae Hong , Lynn Youngs
IPC: H05K3/10
CPC classification number: G06F3/0416 , G06F3/044 , H05K1/0306 , H05K3/0097 , H05K2201/0317 , H05K2201/0326 , H05K2203/1536 , Y10T29/49126 , Y10T29/49128 , Y10T29/49147 , Y10T29/49155 , Y10T29/49156
Abstract: A method for fabricating thin DITO or SITO touch sensor panels with a thickness less than a minimum thickness tolerance of existing manufacturing equipment. In one embodiment, a sandwich of two thin glass sheets is formed such that the combined thickness of the glass sheets does not drop below the minimum thickness tolerance of existing manufacturing equipment when thin film process is performed on the surfaces of the sandwich during fabrication. The sandwich may eventually be separated to form two thin SITO/DITO panels. In another embodiment, the fabrication process involves laminating two patterned thick substrates, each having at least the minimum thickness tolerance of existing manufacturing equipment. One or both of the sides of the laminated substrates are then thinned so that when the substrates are separated, each is a thin DITO/SITO panel having a thickness less than the minimum thickness tolerance of existing manufacturing equipment.
Abstract translation: 用于制造厚度小于现有制造设备的最小厚度公差的薄DITO或SITO触摸传感器面板的方法。 在一个实施例中，形成两个薄玻璃板的夹层，使得当在制造期间在夹层的表面上执行薄膜处理时，玻璃板的组合厚度不会下降到现有制造设备的最小厚度公差之下。 三明治可能最终分开形成两个薄的SITO / DITO面板。 在另一个实施例中，制造工艺包括层压两个图案化的厚基板，每个基板至少具有现有制造设备的最小厚度公差。 然后层压基板的一个或两个侧面变薄，使得当基板分离时，每个是具有小于现有制造设备的最小厚度公差的厚度的薄DITO / SITO面板。
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公开(公告)号：US07877866B1
公开(公告)日：2011-02-01
申请号：US11545354
申请日：2006-10-10
Applicant: Robert J. Greenberg , Neil Hamilton Talbot , Jordan Matthew Neysmith , Jerry Ok
Inventor： Robert J. Greenberg , Neil Hamilton Talbot , Jordan Matthew Neysmith , Jerry Ok
CPC classification number: H05K3/06 , A61N1/0543 , H05K1/118 , H05K3/0041 , H05K3/28 , H05K3/381 , H05K3/388 , H05K2201/0154 , H05K2201/0317 , H05K2203/0554 , H05K2203/0789 , H05K2203/0793 , H05K2203/095 , H05K2203/1163 , Y10T29/49124 , Y10T29/49147 , Y10T29/49155
Abstract: A method of manufacturing a flexible circuit electrode array that provides excellent adhesion between the polymer base layer and the polymer top layer and insulation of the trace metals and electrodes. A layer of polymer is laid down. A layer of metal is applied to the polymer and patterned to create electrodes and leads for those electrodes. A second layer of polymer is applied over the metal layer and patterned to leave openings for the electrodes, or openings are created later by means such as laser ablation. Hence the array and its supply cable are formed of a single body. Alternatively, multiple alternating layers of metal and polymer may be applied to obtain more metal traces within a given width.
Abstract translation: 一种制造柔性电路电极阵列的方法，其提供聚合物基层和聚合物顶层之间的优异粘附性以及痕量金属和电极的绝缘。 放置一层聚合物。 将一层金属施加到聚合物上并图案化以产生用于那些电极的电极和引线。 将第二层聚合物施加在金属层上并图案化以留下电极的开口，或稍后通过诸如激光烧蚀的手段产生开口。 因此阵列及其供电电缆由单体形成。 或者，可以施加金属和聚合物的多个交替层以在给定宽度内获得更多的金属迹线。
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公开(公告)号：US20100175249A1
公开(公告)日：2010-07-15
申请号：US12351767
申请日：2009-01-09
Applicant: Shih Chang CHANG , John Z. Zhong , Lili Huang , Seung Jae Hong , Lynn Youngs
Inventor： Shih Chang CHANG , John Z. Zhong , Lili Huang , Seung Jae Hong , Lynn Youngs
IPC: H05K3/10
CPC classification number: G06F3/0416 , G06F3/044 , H05K1/0306 , H05K3/0097 , H05K2201/0317 , H05K2201/0326 , H05K2203/1536 , Y10T29/49126 , Y10T29/49128 , Y10T29/49147 , Y10T29/49155 , Y10T29/49156
Abstract: A method for fabricating thin DITO or SITO touch sensor panels with a thickness less than a minimum thickness tolerance of existing manufacturing equipment. In one embodiment, a sandwich of two thin glass sheets is formed such that the combined thickness of the glass sheets does not drop below the minimum thickness tolerance of existing manufacturing equipment when thin film process is performed on the surfaces of the sandwich during fabrication. The sandwich may eventually be separated to form two thin SITO/DITO panels. In another embodiment, the fabrication process involves laminating two patterned thick substrates, each having at least the minimum thickness tolerance of existing manufacturing equipment. One or both of the sides of the laminated substrates are then thinned so that when the substrates are separated, each is a thin DITO/SITO panel having a thickness less than the minimum thickness tolerance of existing manufacturing equipment.
Abstract translation: 用于制造厚度小于现有制造设备的最小厚度公差的薄DITO或SITO触摸传感器面板的方法。 在一个实施例中，形成两个薄玻璃板的夹层，使得当在制造期间在夹层的表面上执行薄膜处理时，玻璃板的组合厚度不会下降到现有制造设备的最小厚度公差之下。 三明治可能最终分开形成两个薄的SITO / DITO面板。 在另一个实施例中，制造工艺包括层压两个图案化的厚基板，每个基板至少具有现有制造设备的最小厚度公差。 然后层压基板的一个或两个侧面变薄，使得当基板分离时，每个是具有小于现有制造设备的最小厚度公差的厚度的薄DITO / SITO面板。
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公开(公告)号：US07754416B2
公开(公告)日：2010-07-13
申请号：US11720180
申请日：2005-11-28
Applicant: Koichi Misumi , Koji Saito , Kaoru Ishikawa
Inventor： Koichi Misumi , Koji Saito , Kaoru Ishikawa
CPC classification number: H05K3/108 , G03F7/0397 , G03F7/11 , H05K3/384 , H05K2201/0317
Abstract: This process for producing a resist pattern includes: the step of laminating (a) a support having an upper surface on which copper exists, (b) an inorganic substance layer consisting of an inorganic substance supplied from an inorganic substance source, and (c) a photoresist layer consisting of a chemically amplified type positive photoresist composition, to obtain a photoresist laminate, the step of selectively irradiating active light or radioactive rays to said photoresist laminate, and the step of developing said (c) photoresist layer together with said (b) inorganic substance layer to form a resist pattern.
Abstract translation: 制造抗蚀剂图案的方法包括：（a）具有铜的上表面的载体的层叠步骤，（b）由无机物质源供给的无机物质构成的无机物质层，（c） 由化学放大型正性光致抗蚀剂组合物构成的光致抗蚀剂层，以获得光致抗蚀剂层压体，选择性地向所述光致抗蚀剂层压体照射活性光或放射线的步骤，以及将所述（c）光致抗蚀剂层与所述（b ）无机物质层以形成抗蚀剂图案。
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Patent Agency Ranking
246.发明申请公开(公告)号：US20100090781A1
公开(公告)日：2010-04-15
申请号：US11997178
申请日：2006-09-22
Applicant: Kenichi Yamamoto , Daido Komyoji , Keizaburo Kuramasu
Inventor： Kenichi Yamamoto , Daido Komyoji , Keizaburo Kuramasu
CPC classification number: H05K1/16 , H01L23/66 , H01L27/016 , H01L2924/0002 , H03H7/0115 , H03H7/175 , H05K1/162 , H05K1/165 , H05K3/4614 , H05K2201/0317 , H05K2201/086 , H05K2201/09763 , H05K2203/1189 , Y10T29/49155 , H01L2924/00
Abstract: To provide a configuration including a first sheet substrate, on which a first thin film electronic component is formed on at least one main face, and an external connection terminal for connecting to an external circuit is formed one main face or the other face; a second sheet substrate, on which a second thin film electronic component is formed on at least one face; an insulator connection resin layer for fixing the first sheet substrate and the second sheet substrate opposing the first thin film electronic component against the second thin film electronic component; and an interlayer connection conductor for electrically connecting electrode terminals, which have been set in advance, of the first thin film electronic component and the second thin film electronic component.
Abstract translation: 为了提供一种构造，其包括在至少一个主面上形成有第一薄膜电子部件的第一片状基板和用于连接到外部电路的外部连接端子，形成为一个主面或另一个面; 第二片基板，在至少一个面上形成有第二薄膜电子部件; 绝缘体连接树脂层，用于将第一薄片基板和与第一薄膜电子部件相对的第二薄片基板固定在第二薄膜电子部件上; 以及用于电连接第一薄膜电子部件和第二薄膜电子部件的预先设定的电极端子的层间连接导体。
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公开(公告)号：US07566833B2
公开(公告)日：2009-07-28
申请号：US11439307
申请日：2006-05-24
Applicant: Jun Ishii , Yasuhito Funada , Yasunari Ooyabu
Inventor： Jun Ishii , Yasuhito Funada , Yasunari Ooyabu
IPC: H05K1/00
CPC classification number: H05K1/0259 , H05K1/056 , H05K1/167 , H05K3/28 , H05K2201/0317 , H05K2203/0315 , Y10T428/24917 , Y10T428/24926
Abstract: A wired circuit board that can remove static electricity not only from an insulating base layer and an insulating cover layer but also from a terminal portion, to effectively prevent an electronic component mounted from being damaged by static electricity and also prevent stripping of a semi-conductive layer. In a suspension board with circuit including an insulating base layer formed on a metal supporting board, a conductive pattern formed on the insulating base layer, and an insulating cover layer, formed on the insulating cover layer, to cover the conductive pattern and form an opening, semi-conductive layer is formed in succession on an upper surface of the insulating base layer covered with the insulating cover layer, on a lateral side surface and an upper surface of the conductive pattern, and on a lateral side surface of the insulating base layer adjacent to the metal supporting board.
Abstract translation: 一种布线电路板，其不仅可以从绝缘基层和绝缘覆盖层，而且从端子部分去除静电，以有效地防止安装的电子部件被静电损坏，并且还防止半导体剥离 层。 在具有形成在金属支撑基板上的绝缘基底层的电路的悬挂基板上，形成在绝缘基底层上的导电图案和形成在绝缘覆盖层上的绝缘覆盖层，以覆盖导电图案并形成开口 在覆盖有绝缘覆盖层的绝缘基底层的上表面上，在导电图案的侧面和上表面上以及绝缘基底层的侧面上依次形成半导体层 毗邻金属支撑板。
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公开(公告)号：US07514038B2
公开(公告)日：2009-04-07
申请号：US10861976
申请日：2004-06-04
Applicant: Shaun Pendo , Rajiv Shah , Edward Chernoff
Inventor： Shaun Pendo , Rajiv Shah , Edward Chernoff
CPC classification number: H05K3/28 , A61B5/0006 , H05K1/0306 , H05K3/4061 , H05K2201/0175 , H05K2201/0179 , H05K2201/0317 , H05K2201/09472 , H05K2203/082 , H05K2203/085 , H05K2203/1147 , H05K2203/1476 , H05K2203/1572 , H05K2203/308
Abstract: A substrate with hermetically sealed vias extending from one side of the substrate to another and a method for fabricating same. The vias may be filled with a conductive material such as, for example, a fritless ink. The conductive path formed by the conductive material aids in sealing one side of the substrate from another. One side of the substrate may include a sensing element and another side of the substrate may include sensing electronics.
Abstract translation: 具有从衬底的一侧延伸到另一侧的气密密封通孔的衬底及其制造方法。 通孔可以填充有导电材料，例如无油墨。 由导电材料形成的导电路径有助于将基板的一侧与另一侧密封。 衬底的一侧可以包括感测元件，并且衬底的另一侧可以包括感测电子器件。
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249.发明申请公开(公告)号：US20080315901A1
公开(公告)日：2008-12-25
申请号：US12099691
申请日：2008-04-08
Applicant: Tatsuo INOUE , Osamu ARAI , Katsushi MIKUNI , Norihiro IMAI
Inventor： Tatsuo INOUE , Osamu ARAI , Katsushi MIKUNI , Norihiro IMAI
CPC classification number: H05K1/167 , G01R1/06766 , G01R1/07342 , H05K3/0023 , H05K3/108 , H05K3/467 , H05K2201/0317 , H05K2201/0352 , H05K2201/09781 , H05K2203/025 , H05K2203/1453 , Y10T29/49099 , Y10T29/49155 , Y10T29/49165
Abstract: The present invention provides a multilayer wiring board in which resistive elements each of whose error from a desired value is smaller than in a conventional case are built, a method for manufacturing the same, and a probe apparatus utilizing the multilayer wiring board. The present invention is based on a basic concept of forming a flat surface on a surface of a multilayer wiring layer on which a resistive element material is to be deposited and depositing the resistive element material on the flat surface. The multilayer wiring board comprises a multilayer wiring layer on whose surface convexo-concave is formed, a dummy layer burying the convexo-concave within a desired area of the surface of the multilayer wiring layer and having an approximately flat surface, a resistance material layer made of an electrical resistance material deposited on the dummy layer and at an area going beyond the dummy layer, and a wire made of a conductive material deposited on the resistance material layer and ranging from the area going beyond the dummy layer to a part of the flat surface area of the dummy layer, wherein a resistive element is formed at an area of the resistance material layer that the wire does not reach.
Abstract translation: 本发明提供了一种多层布线板，其中构成了每个误差小于常规情况的电阻元件，其制造方法和利用多层布线板的探针装置。 本发明基于在其上要沉积电阻元件材料的多层布线层的表面上形成平坦表面的基本概念，并将电阻元件材料沉积在平坦表面上。 多层布线基板包括在其表面形成凹凸的多层布线层，在多层布线层的表面的期望区域内埋入凸凹并具有大致平坦表面的虚拟层，制成的电阻材料层 沉积在虚设层和超过虚设层的区域上的电阻材料以及由电阻材料层上沉积的导电材料制成的导线并且从超出虚设层的区域延伸到平坦部分的一部分 虚拟层的表面积，其中电阻元件形成在电阻材料层的未到达的区域。
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250.发明授权公开(公告)号：US07446388B2
公开(公告)日：2008-11-04
申请号：US11284704
申请日：2005-11-21
Applicant: Michael D. Casper , William B. Mraz
Inventor： Michael D. Casper , William B. Mraz
IPC: H01L21/00
CPC classification number: H01L21/4846 , H01L23/15 , H01L23/49822 , H01L25/16 , H01L27/016 , H01L2924/0002 , H01L2924/09701 , H01L2924/19011 , H01Q21/061 , H05K1/16 , H05K1/162 , H05K1/165 , H05K3/002 , H05K3/4644 , H05K3/467 , H05K2201/0179 , H05K2201/0317 , H05K2201/09763 , H01L2924/00
Abstract: A system and method for the fabrication of high reliability capacitors (1011), inductors (1012), and multi-layer interconnects (1013) (including resistors (1014)) on various thin film hybrid substrate surfaces (0501) is disclosed. The disclosed method first employs a thin metal layer (0502) deposited and patterned on the substrate (0501). This thin patterned layer (0502) is used to provide both lower electrodes for capacitor structures (0603) and interconnects (0604) between upper electrode components. Next, a dielectric layer (0705) is deposited over the thin patterned layer (0502) and the dielectric layer (0705) is patterned to open contact holes (0806) to the thin patterned layer. The upper electrode layers (0907, 0908, 1009, 1010) are then deposited and patterned on top of the dielectric (0705).
Abstract translation: 公开了用于在各种薄膜混合基板表面（0501）上制造高可靠性电容器（1011），电感器（1012）和多层互连（1013）（包括电阻器（1014））的系统和方法。 所公开的方法首先采用在衬底（0501）上沉积和图案化的薄金属层（0502）。 该薄图案层（0502）用于为上电极组件之间的电容器结构（0603）和互连（0604）提供两个下电极。 接下来，在薄的图案化层（0502）上沉积电介质层（0705），并且对电介质层（0705）进行图案化以将薄的图案化层的接触孔（0806）打开。 然后将上电极层（0907,0908,1009,1010）沉积并图案化在电介质（0705）的顶部。
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