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公开(公告)号：US20240162178A1
公开(公告)日：2024-05-16
申请号：US18422795
申请日：2024-01-25
Inventor： Javier A. DeLaCruz , Belgacem Haba , Jung Ko
IPC: H01L23/00 , G01R31/27 , G01R31/28 , H01L25/065
CPC classification number: H01L24/06 , G01R31/275 , G01R31/2856 , H01L24/08 , H01L25/0657
Abstract: A bonded structure is disclosed. The bonded structure can include a first element that has a first plurality of contact pads. The first plurality of contact pads includes a first contact pad and a second redundant contact pad. The bonded structure can also include a second element directly bonded to the first element without an intervening adhesive. The second element has a second plurality of contact pads. The second plurality of contact pads includes a third contact pad and a fourth redundant contact pad. The first contact pad is configured to connect to the third contact pad. The second contact pad is configured to connect to the fourth contact pad. The bonded structure can include circuitry that has a first state in which an electrical signal is transferred to the first contact pad and a second state in which the electrical signal is transferred to the second contact pad.
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公开(公告)号：US20240162102A1
公开(公告)日：2024-05-16
申请号：US18545120
申请日：2023-12-19
Inventor： Rajesh Katkar , Liang Wang
CPC classification number: H01L23/26 , B81B7/0038 , B81C3/001 , H01L21/3221 , H01L23/04 , H01L23/10 , H01L24/03 , H01L24/09
Abstract: A bonded structure is disclosed. The bonded structure can include a first element that has a first bonding surface. The bonded structure can further include a second element that has a second bonding surface. The first and second bonding surfaces are bonded to one another along a bonding interface. The bonded structure can also include an integrated device that is coupled to or formed with the first element or the second element. The bonded structure can further include a channel that is disposed along the bonding interface around the integrated device to define an effectively closed profile The bonded structure can also include a getter material that is disposed in the channel. The getter material is configured to reduce the diffusion of gas into an interior region of the bonded structure.
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公开(公告)号：US20240136333A1
公开(公告)日：2024-04-25
申请号：US18535375
申请日：2023-12-11
Inventor： Rajesh Katkar , Belgacem Haba
IPC: H01L25/065 , H01L23/00
CPC classification number: H01L25/0657 , H01L24/06 , H01L24/26 , H01L24/93
Abstract: An element that is configured to bond to another element is disclosed. A first element that can include a first plurality of contact pads on a first surface. The first plurality of contact pads includes a first contact pad and a second contact pad that are spaced apart from one another. The first and second contact pads are electrically connected to one another for redundancy. The first element can be prepared for direct bonding. The first element can be bonded to a second element to form a bonded structure. The second element has a second plurality of contact pads on a second surface. At least one of the second plurality of contact pads is bonded and electrically connected to at least one of the first plurality of contact pads.
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公开(公告)号：US11955445B2
公开(公告)日：2024-04-09
申请号：US17836840
申请日：2022-06-09
Inventor： Guilian Gao , Bongsub Lee , Gaius Gillman Fountain, Jr. , Cyprian Emeka Uzoh , Laura Wills Mirkarimi , Belgacem Haba , Rajesh Katkar
IPC: H01L23/00 , H01L21/768 , H01L23/48 , H01L25/00 , H01L25/065
CPC classification number: H01L24/08 , H01L21/76898 , H01L23/481 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/09 , H01L24/80 , H01L25/0657 , H01L25/50 , H01L24/94 , H01L2224/05147 , H01L2224/05181 , H01L2224/05184 , H01L2224/08146 , H01L2224/80896
Abstract: Representative techniques and devices including process steps may be employed to mitigate the potential for delamination of bonded microelectronic substrates due to metal expansion at a bonding interface. For example, a metal pad having a larger diameter or surface area (e.g., oversized for the application) may be used when a contact pad is positioned over a TSV in one or both substrates.
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公开(公告)号：US20240105674A1
公开(公告)日：2024-03-28
申请号：US18461372
申请日：2023-09-05
Inventor： Cyprian Emeka Uzoh , Thomas Workman
IPC: H01L23/00
CPC classification number: H01L24/80 , H01L24/05 , H01L24/08 , H01L2224/05647 , H01L2224/08145 , H01L2224/80031 , H01L2224/80047 , H01L2224/80365 , H01L2224/80379 , H01L2224/80896 , H01L2924/04642 , H01L2924/0504 , H01L2924/0544 , H01L2924/059
Abstract: Bonded structures and methods of forming a bonded structure are disclosed. A bonded structure can include a first element and a second element. The first element includes a first non-conductive field region and a first conductive feature. The second element includes a second non-conductive field region and a second conductive feature. The second element is directly bonded to the first element along a bonding interface such that the first non-conductive field region is directly bonded to the second non-conductive field region without an intervening adhesive, and the first conductive feature is directly bonded to the second conductive feature without an intervening adhesive. A first portion of the first non-conductive field region at the bonding interface has a first surface roughness and a second portion of the first non-conductive field region at the bonding interface has a second surface roughness. The second surface roughness can be different from the first surface roughness. The first surface roughness can be greater than 6 Å rms.
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Patent Agency Ranking
公开(公告)号：US20240103274A1
公开(公告)日：2024-03-28
申请号：US18360193
申请日：2023-07-27
Inventor： Rajesh Katkar , Belgacem Haba
IPC: G02B27/01 , G02B27/10 , G02B27/14 , H01L25/075
CPC classification number: G02B27/0172 , G02B27/102 , G02B27/141 , H01L25/0753 , G02B2027/0178
Abstract: A bonded optical device is disclosed. The bonded optical device can include a first optical element, a second optical element, and an optical pathway. The first optical element has a first array of optical emitters configured to emit light of a first color. The first optical element is bonded to at least one processor element, the at least one processor element including active circuitry configured to control operation of the first optical element. The second optical element has a second array of optical emitters configured to emit light of a second color different from the first color. The second optical element is bonded to the at least one processor element. The optical pathway is optically coupled with the first and second optical elements. The optical pathway is configured to transmit a superposition of light from the first and second optical emitters to an optical output to be viewed by users.
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公开(公告)号：US20240088120A1
公开(公告)日：2024-03-14
申请号：US18507478
申请日：2023-11-13
Inventor： Paul M. Enquist , Belgacem Haba
IPC: H01L25/00 , H01L21/768 , H01L21/822 , H01L23/00 , H01L23/31 , H01L23/48 , H01L25/07 , H01L25/18 , H01L27/146
CPC classification number: H01L25/50 , H01L21/76898 , H01L21/8221 , H01L23/3171 , H01L23/481 , H01L24/09 , H01L25/074 , H01L25/18 , H01L27/14618 , H01L27/14621 , H01L27/14627 , H01L27/14632 , H01L27/14634 , H01L27/14636 , H01L27/14687 , H01L27/1469 , H01L2224/02379 , H01L2924/1431 , H01L2924/1434
Abstract: Stacked devices and methods of fabrication are provided. Die-to-wafer (D2W) direct-bonding techniques join layers of dies of various physical sizes, form factors, and foundry nodes to a semiconductor wafer, to interposers, or to boards and panels, allowing mixing and matching of variegated dies in the fabrication of 3D stacked devices during wafer level packaging (WLP). Molding material fills in lateral spaces between dies to enable fan-out versions of 3D die stacks with fine pitch leads and capability of vertical through-vias throughout. Molding material is planarized to create direct-bonding surfaces between multiple layers of the variegated dies for high interconnect density and reduction of vertical height. Interposers with variegated dies on one or both sides can be created and bonded to wafers. Logic dies and image sensors from different fabrication nodes and different wafer sizes can be stacked during WLP, or logic dies and high bandwidth memory (HBM) of different geometries can be stacked during WLP.
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公开(公告)号：US20240079351A1
公开(公告)日：2024-03-07
申请号：US18346396
申请日：2023-07-03
Inventor： Javier A. DeLaCruz , Rajesh Katkar
IPC: H01L23/00
CPC classification number: H01L23/573 , H01L24/05 , H01L24/48 , H01L24/83 , H01L24/94 , H01L2224/04042 , H01L2224/83896
Abstract: A bonded structure is disclosed. The bonded structure can include a semiconductor element comprising active circuitry. The bonded structure can include an obstructive element bonded to the semiconductor element along a bond interface, the obstructive element including an obstructive material disposed over the active circuitry, the obstructive material configured to obstruct external access to the active circuitry. The bonded element can include an artifact structure indicative of a wafer-level bond in which the semiconductor element and the obstructive element formed part of respective wafers directly bonded prior to singulation.
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公开(公告)号：US11894326B2
公开(公告)日：2024-02-06
申请号：US17370576
申请日：2021-07-08
Inventor： Rajesh Katkar , Cyprian Emeka Uzoh
CPC classification number: H01L24/05 , H01L24/03 , H01L24/08 , H01L24/80 , H01L25/50 , H01L2224/0347 , H01L2224/0362 , H01L2224/0384 , H01L2224/03462 , H01L2224/03464 , H01L2224/03616 , H01L2224/03845 , H01L2224/05013 , H01L2224/05015 , H01L2224/05026 , H01L2224/05076 , H01L2224/05082 , H01L2224/05105 , H01L2224/05109 , H01L2224/05111 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05171 , H01L2224/05181 , H01L2224/05551 , H01L2224/05554 , H01L2224/05555 , H01L2224/05576 , H01L2224/05578 , H01L2224/05605 , H01L2224/05609 , H01L2224/05611 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/08145 , H01L2224/08146 , H01L2224/80375 , H01L2224/80895 , H01L2224/05647 , H01L2924/00014 , H01L2224/05655 , H01L2924/00014 , H01L2224/05611 , H01L2924/00014 , H01L2224/05609 , H01L2924/00014 , H01L2224/05605 , H01L2924/00014 , H01L2224/05644 , H01L2924/00014 , H01L2224/05639 , H01L2924/00014
Abstract: A first conductive material having a first hardness is disposed within a recess or opening of a microelectronic component, in a first preselected pattern, and forms a first portion of an interconnect structure. A second conductive material having a second hardness different from the first hardness is disposed within the recess or opening in a second preselected pattern and forms a second portion of the interconnect structure.
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公开(公告)号：US20240021573A1
公开(公告)日：2024-01-18
申请号：US18353019
申请日：2023-07-14
Inventor： Cyprian Emeka Uzoh , Pawel Mrozek
IPC: H01L23/00
CPC classification number: H01L24/80 , H01L24/08 , H01L2224/08145 , H01L2224/80896 , H01L2224/80013 , H01L2224/80031 , H01L2224/80895 , H01L2224/80011
Abstract: Reliable hybrid bonded apparatuses are provided. An example process cleans nanoparticles from at least the smooth oxide top layer of a surface to be hybrid bonded after the surface has already been activated for the hybrid bonding. Conventionally, such an operation is discouraged. However, the example cleaning processes described herein increase the electrical reliability of microelectronic devices. Extraneous metal nanoparticles can enable undesirable current and signal leakage from finely spaced traces, especially at higher voltages with ultra-fine trace pitches. In the example process, the extraneous nanoparticles may be both physically removed and/or dissolved without detriment to the activated bonding surface.
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