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公开(公告)号：US20250037361A1
公开(公告)日：2025-01-30
申请号：US18913688
申请日：2024-10-11
Applicant: Imagination Technologies Limited
Inventor： Jens Fursund , Luke T. Peterson
IPC: G06T15/80
Abstract: Rendering systems that can use combinations of rasterization rendering processes and ray tracing rendering processes are disclosed. In some implementations, these systems perform a rasterization pass to identify visible surfaces of pixels in an image. Some implementations may begin shading processes for visible surfaces, before the geometry is entirely processed, in which rays are emitted. Rays can be culled at various points during processing, based on determining whether the surface from which the ray was emitted is still visible. Rendering systems may implement rendering effects as disclosed.
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22.发明授权公开(公告)号：US12211135B2
公开(公告)日：2025-01-28
申请号：US18239699
申请日：2023-08-29
Applicant: Imagination Technologies Limited
Inventor： Simon Fenney , Rostam King , Peter Smith-Lacey , Gregory Clark
Abstract: A method and an intersection testing module in a ray tracing system for determining whether a ray intersects a three-dimensional axis-aligned box. It is determined whether a first condition is satisfied, wherein the first condition is, or is equivalent to, ❘ "\[LeftBracketingBar]" C x - C z D x D z ❘ "\[RightBracketingBar]" ≤ H z D x D z + H x . It is determined whether a second condition is satisfied, wherein the second condition is, or is equivalent to, ❘ "\[LeftBracketingBar]" C y - C z D y D z ❘ "\[RightBracketingBar]" ≤ H z D y D z + H y . It is determined whether a third condition is satisfied, wherein the third condition is, or is equivalent to, ❘ "\[LeftBracketingBar]" C x D y D z - C y D x D z ❘ "\[RightBracketingBar]" ≤ H y D x D z + H x D y D z The determinations of whether the first, second and third conditions are satisfied are used to determine whether the ray intersects the axis-aligned box. Cx, Cy and Cz are x, y and z components of a position of the centre of the axis-aligned box relative to an origin of the ray, Hx, Hy and Hz are half widths of the axis-aligned box in the x, y and z dimensions, and Dx, Dy and Dz are x, y and z components of a direction vector of the ray.
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公开(公告)号：US20250021340A1
公开(公告)日：2025-01-16
申请号：US18439700
申请日：2024-02-12
Applicant: Imagination Technologies Limited
Inventor： Luca Iuliano , Simon Nield , Yoong-Chert Foo , Ollie Mower
Abstract: Methods and parallel processing units for avoiding inter-pipeline data hazards identified at compile time. For each identified inter-pipeline data hazard the primary instruction and secondary instruction(s) thereof are identified as such and are linked by a counter which is used to track that inter-pipeline data hazard. When a primary instruction is output by the instruction decoder for execution the value of the counter associated therewith is adjusted to indicate that there is hazard related to the primary instruction, and when primary instruction has been resolved by one of multiple parallel processing pipelines the value of the counter associated therewith is adjusted to indicate that the hazard related to the primary instruction has been resolved. When a secondary instruction is output by the decoder for execution, the secondary instruction is stalled in a queue associated with the appropriate instruction pipeline if at least one counter associated with the primary instructions from which it depends indicates that there is a hazard related to the primary instruction.
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公开(公告)号：US12198307B2
公开(公告)日：2025-01-14
申请号：US17956778
申请日：2022-09-29
Applicant: Imagination Technologies Limited
Inventor： Szabolcs Cséfalvay , James Imber , David Walton , Insu Yu
Abstract: A method of rendering an image of a 3-D scene includes rendering a noisy image at a first resolution; obtaining one or more guide channels at the first resolution, and obtaining one or more corresponding guide channels at a second resolution. The second resolution may be the same resolution as, or a higher resolution than, the first resolution. For each of a plurality of local neighbourhoods, the method comprises: calculating the parameters of a model that approximates the noisy image as a function of the one or more guide channels (at the first resolution), and applying the calculated parameters to the one or more guide channels at the second resolution, to produce a denoised image at the second resolution.
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公开(公告)号：US12190432B2
公开(公告)日：2025-01-07
申请号：US18239224
申请日：2023-08-29
Applicant: Imagination Technologies Limited
Inventor： Casper Van Benthem
Abstract: A graphics processing hardware pipeline is arranged to perform an edge test or a depth calculation. Each hardware arrangement includes a microtile component hardware element, multiple pixel component hardware elements, one or more subsample component hardware elements and a final addition and comparison unit. The microtile component hardware element calculates a first output using a sum-of-products and coordinates of a microtile within a tile in the rendering space. Each pixel component hardware element calculates a different second output using the sum-of-products and coordinates for different pixels defined relative to an origin of the microtile. The subsample component hardware element calculates a third output using the sum-of-products and coordinates for a subsample position defined relative to an origin of a pixel. The adders sum different combinations of the first output, a second output and a third output to generate output results for different subsample positions defined relative to the origin of the tile.
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Patent Agency Ranking
公开(公告)号：US12190035B2
公开(公告)日：2025-01-07
申请号：US17501666
申请日：2021-10-14
Applicant: Imagination Technologies Limited
Inventor： Rachel Edmonds , Sam Elliott
IPC: G06F30/3323 , G06F119/16
Abstract: Methods and systems for verifying a hardware design for an integrated circuit that implements a function that is polynomial of degree k in a sub-function p over a set of values of p, k being an integer greater than or equal to one. The methods include: verifying that an instantiation of the hardware design correctly evaluates the sub-function p; formally verifying that an instantiation of the hardware design implements a function that is polynomial of degree k in p by formally verifying that, for all values of p in the set of values of p, an instantiation of the hardware design has a constant kth difference; and verifying that an instantiation of the hardware design generates an expected output in response to each of at least e different values of p in the set of values of p, wherein e is equal to k when a value of the kth difference is predetermined and e is equal to k+1 when the value of the kth difference is not predetermined.
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公开(公告)号：US20240428504A1
公开(公告)日：2024-12-26
申请号：US18823556
申请日：2024-09-03
Applicant: Imagination Technologies Limited
Inventor： John W. Howson , Steven J. Clohset , Ali Rabbani
Abstract: A ray tracing unit implemented in a graphics rendering system includes processing logic configured to perform ray tracing operations on rays, a dedicated ray memory coupled to the processing logic and configured to store ray data for rays to be processed by the processing logic, an interface to a memory system, and control logic configured to manage allocation of ray data to either the dedicated ray memory or the memory system. Core ray data for rays to be processed by the processing logic is stored in the dedicated ray memory, and at least some non-core ray data for the rays is stored in the memory system. This allows core ray data for many rays to be stored in the dedicated ray memory without the size of the dedicated ray memory becoming too wasteful when the ray tracing unit is not in use.
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公开(公告)号：US12175179B2
公开(公告)日：2024-12-24
申请号：US18076231
申请日：2022-12-06
Applicant: Imagination Technologies Limited
Inventor： Ashish Darbari , Iain Singleton
IPC: G06F30/3323 , G06F11/30 , G06F11/34 , G06F11/36 , G06F30/30 , G06F30/39 , G06F30/398 , G06F119/18
Abstract: A hardware monitor arranged to assess performance of a hardware design for an integrated circuit to complete a task. The hardware monitor includes monitoring and counting logic configured to count a number of cycles between start and completion of the symbolic task in the hardware design; and property evaluation logic configured to evaluate one or more formal properties related to the counted number of cycles to assess the performance of the hardware design in completing the symbolic task. The hardware monitor may be used by a formal verification tool to exhaustively verify that the hardware design meets a desired performance goal and/or to exhaustively identify a performance metric (e.g. best case and/or worst case performance) with respect to completion of the task.
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公开(公告)号：US12169700B2
公开(公告)日：2024-12-17
申请号：US18241977
申请日：2023-09-04
Applicant: Imagination Technologies Limited
Inventor： Theo Alan Drane , Wai-Chuen Cheung
IPC: G06F7/535 , G06F7/38 , G06F30/00 , G06F30/30 , G06F30/327
Abstract: A method and apparatus are provided for manufacturing integrated circuits performing invariant integer division x/d. A desired rounding mode is provided and an integer triple (a,b,k) for this rounding mode is derived. Furthermore, a set of conditions for the rounding mode is derived. An RTL representation is then derived using the integer triple. From this a hardware layout can be derived and an integrated circuit manufactured with the derived hardware layout. When the integer triple is derived a minimum value of k for the desired rounding mode and set of conditions is also derived.
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公开(公告)号：US12165278B2
公开(公告)日：2024-12-10
申请号：US17479935
申请日：2021-09-20
Applicant: Imagination Technologies Limited
Inventor： Timothy Lee , Alan Vines , David Hough
Abstract: A hardware downscaling module and downscaling methods for downscaling a two-dimensional array of values. The hardware downscaling unit comprises a first group of one-dimensional downscalers; and a second group of one-dimensional downscalers; wherein the first group of one-dimensional downscalers is arranged to receive a two-dimensional array of values and to perform downscaling in series in a first dimension; and wherein the second group of one-dimensional downscalers is arranged to receive an output from the first group of one-dimensional downscalers and to perform downscaling in series in a second dimension.
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