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公开(公告)号：US20250021340A1
公开(公告)日：2025-01-16
申请号：US18439700
申请日：2024-02-12
Applicant: Imagination Technologies Limited
Inventor： Luca Iuliano , Simon Nield , Yoong-Chert Foo , Ollie Mower
Abstract: Methods and parallel processing units for avoiding inter-pipeline data hazards identified at compile time. For each identified inter-pipeline data hazard the primary instruction and secondary instruction(s) thereof are identified as such and are linked by a counter which is used to track that inter-pipeline data hazard. When a primary instruction is output by the instruction decoder for execution the value of the counter associated therewith is adjusted to indicate that there is hazard related to the primary instruction, and when primary instruction has been resolved by one of multiple parallel processing pipelines the value of the counter associated therewith is adjusted to indicate that the hazard related to the primary instruction has been resolved. When a secondary instruction is output by the decoder for execution, the secondary instruction is stalled in a queue associated with the appropriate instruction pipeline if at least one counter associated with the primary instructions from which it depends indicates that there is a hazard related to the primary instruction.
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公开(公告)号：US20230376348A1
公开(公告)日：2023-11-23
申请号：US18228545
申请日：2023-07-31
Applicant: Imagination Technologies Limited
Inventor： Simon Nield , Adam de Grasse , Luca Iuliano , Ollie Mower , Yoong-Chert Foo
CPC classification number: G06F9/4881 , G06F1/329 , G06F9/4893 , G06F9/5027 , G06F2209/483 , G06F2209/486 , G06T1/20
Abstract: A method of scheduling tasks within a GPU or other highly parallel processing unit is described which is both age-aware and wakeup event driven. Tasks which are received are added to an age-based task queue. Wakeup event bits for task types, or combinations of task types and data groups, are set in response to completion of a task dependency and these wakeup event bits are used to select an oldest task from the queue that satisfies predefined criteria.
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公开(公告)号：US20230097760A1
公开(公告)日：2023-03-30
申请号：US18075394
申请日：2022-12-05
Applicant: Imagination Technologies Limited
Inventor： Simon Nield , Yoong-Chert Foo , Adam de Grasse , Luca Iuliano
Abstract: A method of activating scheduling instructions within a parallel processing unit is described. The method comprises decoding, in an instruction decoder, an instruction in a scheduled task in an active state and checking, by an instruction controller, if a swap flag is set in the decoded instruction. If the swap flag in the decoded instruction is set, a scheduler is triggered to de-activate the scheduled task by changing the scheduled task from the active state to a non-active state.
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公开(公告)号：US11366691B2
公开(公告)日：2022-06-21
申请号：US17108526
申请日：2020-12-01
Applicant: Imagination Technologies Limited
Inventor： Simon Nield , Yoong-Chert Foo , Adam de Grasse , Luca Iuliano
Abstract: A method of scheduling instructions within a parallel processing unit is described. The method comprises decoding, in an instruction decoder, an instruction in a scheduled task in an active state, and checking, by an instruction controller, if an ALU targeted by the decoded instruction is a primary instruction pipeline. If the targeted ALU is a primary instruction pipeline, a list associated with the primary instruction pipeline is checked to determine whether the scheduled task is already included in the list. If the scheduled task is already included in the list, the decoded instruction is sent to the primary instruction pipeline.
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公开(公告)号：US20220091885A1
公开(公告)日：2022-03-24
申请号：US17540009
申请日：2021-12-01
Applicant: Imagination Technologies Limited
Inventor： Simon Nield , Adam de Grasse , Luca Iuliano , Ollie Mower , Yoong-Chert Foo
Abstract: A method of scheduling tasks within a GPU or other highly parallel processing unit is described which is both age-aware and wakeup event driven. Tasks which are received are added to an age-based task queue. Wakeup event bits for task types, or combinations of task types and data groups, are set in response to completion of a task dependency and these wakeup event bits are used to select an oldest task from the queue that satisfies predefined criteria.
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Patent Agency Ranking
公开(公告)号：US20200073713A1
公开(公告)日：2020-03-05
申请号：US16676250
申请日：2019-11-06
Applicant: Imagination Technologies Limited
Inventor： Simon Nield , Adam de Grasse , Luca Iuliano , Ollie Mower , Yoong-Chert Foo
Abstract: A method of scheduling tasks within a GPU or other highly parallel processing unit is described which is both age-aware and wakeup event driven. Tasks which are received are added to an age-based task queue. Wakeup event bits for task types, or combinations of task types and data groups, are set in response to completion of a task dependency and these wakeup event bits are used to select an oldest task from the queue that satisfies predefined criteria.
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公开(公告)号：US20190087229A1
公开(公告)日：2019-03-21
申请号：US16132703
申请日：2018-09-17
Applicant: Imagination Technologies Limited
Inventor： Luca Iuliano , Simon Nield , Yoong-Chert Foo , Ollie Mower , Jonathan Redshaw
Abstract: A memory subsystem for use with a single-instruction multiple-data (SIMD) processor comprising a plurality of processing units configured for processing one or more workgroups each comprising a plurality of SIMD tasks, the memory subsystem comprising: a shared memory partitioned into a plurality of memory portions for allocation to tasks that are to be processed by the processor; and a resource allocator configured to, in response to receiving a memory resource request for first memory resources in respect of a first-received task of a workgroup, allocate to the workgroup a block of memory portions sufficient in size for each task of the workgroup to receive memory resources in the block equivalent to the first memory resources.
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8.发明申请公开(公告)号：US20250156342A1
公开(公告)日：2025-05-15
申请号：US19022210
申请日：2025-01-15
Applicant: Imagination Technologies Limited
Inventor： Luca Iuliano , Simon Nield , Thomas Rose
Abstract: Apparatus identifies a set of M output memory addresses from a larger set of N input memory addresses containing a non-unique memory address. A comparator block performs comparisons of memory addresses from a set of N input memory addresses to generate a binary classification dataset that identifies a subset of addresses, where each address in the subset identified by the binary classification dataset is unique within that subset. Combination logic units receive a selection of bits of the binary classification dataset and sort its received selection of bits into an intermediary binary string in which the bits are ordered into a first group identifying addresses belonging to the identified subset, and a second group identifying addresses not belonging to the identified subset. Output generating logic selects between bits belonging to different intermediary binary strings to generate a binary output identifying a set of output memory addresses containing at least one address in the identified subset.
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公开(公告)号：US11698790B2
公开(公告)日：2023-07-11
申请号：US17523633
申请日：2021-11-10
Applicant: Imagination Technologies Limited
Inventor： Luca Iuliano , Simon Nield , Yoong-Chert Foo , Ollie Mower
CPC classification number: G06F9/3861 , G06F9/3016 , G06F9/3834 , G06F9/3838 , G06F9/3867 , G06F9/3889
Abstract: Methods and parallel processing units for avoiding inter-pipeline data hazards identified at compile time. For each identified inter-pipeline data hazard the primary instruction and secondary instruction(s) thereof are identified as such and are linked by a counter which is used to track that inter-pipeline data hazard. When a primary instruction is output by the instruction decoder for execution the value of the counter associated therewith is adjusted to indicate that there is hazard related to the primary instruction, and when primary instruction has been resolved by one of multiple parallel processing pipelines the value of the counter associated therewith is adjusted to indicate that the hazard related to the primary instruction has been resolved. When a secondary instruction is output by the decoder for execution, the secondary instruction is stalled in a queue associated with the appropriate instruction pipeline if at least one counter associated with the primary instructions from which it depends indicates that there is a hazard related to the primary instruction.
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公开(公告)号：US11656908B2
公开(公告)日：2023-05-23
申请号：US17220849
申请日：2021-04-01
Applicant: Imagination Technologies Limited
Inventor： Luca Iuliano , Simon Nield , Yoong-Chert Foo , Ollie Mower , Jonathan Redshaw
IPC: G06F9/50 , G06F12/084 , G06F12/02 , G06F12/0842 , G06F9/48 , G06F9/54 , G06F12/00
CPC classification number: G06F9/5016 , G06F9/4881 , G06F9/505 , G06F9/5022 , G06F9/544 , G06F12/0223 , G06F12/084 , G06F12/0842 , G06F12/00 , G06F12/02
Abstract: A memory subsystem for use with a single-instruction multiple-data (SIMD) processor comprising a plurality of processing units configured for processing one or more workgroups each comprising a plurality of SIMD tasks, the memory subsystem comprising: a shared memory partitioned into a plurality of memory portions for allocation to tasks that are to be processed by the processor; and a resource allocator configured to, in response to receiving a memory resource request for first memory resources in respect of a first-received task of a workgroup, allocate to the workgroup a block of memory portions sufficient in size for each task of the workgroup to receive memory resources in the block equivalent to the first memory resources.
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