-
公开(公告)号：US20250097400A1
公开(公告)日：2025-03-20
申请号：US18969001
申请日：2024-12-04
Applicant: Imagination Technologies Limited
Inventor： John W. Howson
IPC: H04N13/275 , G06T1/20 , G06T1/60 , H04N13/00 , H04N13/178
Abstract: Methods and graphics processing modules for rendering a stereoscopic image including left and right images of a three-dimensional scene. Geometry is processed in the scene to generate left data for use in displaying the left image and right data for use in displaying the right image. Disparity is determined between the left and right data by comparing the generated left data and the generated right data used in displaying the stereoscopic image. In response to identifying at least a portion of the left data and the right data as non-disparate, a corresponding portion of the left image and the right image is commonly processed (e.g. commonly rendered or commonly stored). In response to identifying at least a portion of the left data and the right data as disparate, a corresponding portion of the left image and the right image is separately processed (e.g. separately rendered or separately stored).
-
公开(公告)号：US20250078384A1
公开(公告)日：2025-03-06
申请号：US18950357
申请日：2024-11-18
Applicant: Imagination Technologies Limited
Inventor： John W. Howson , Richard Broadhurst , Steven Fishwick
Abstract: A graphics processing unit (GPU) processes graphics data using a rendering space which is sub-divided into a plurality of tiles. The GPU comprises cost indication logic configured to obtain a cost indication for each of a plurality of sets of one or more tiles of the rendering space. The cost indication for a set of tile(s) is suggestive of a cost of processing the set of one or more tiles. The GPU controls a rendering complexity with which primitives are rendered in tiles based on the cost indication for those tiles. This allows tiles to be rendered in a manner that is suitable based on the complexity of the graphics data within the tiles. In turn, this allows the rendering to satisfy constraints such as timing constraints even when the complexity of different tiles may vary significantly within an image.
-
公开(公告)号：US12211136B2
公开(公告)日：2025-01-28
申请号：US18102054
申请日：2023-01-26
Applicant: Imagination Technologies Limited
Inventor： John W. Howson , Luke T. Peterson
Abstract: Systems and methods of geometry processing, for rasterization and ray tracing processes provide for pre-processing of source geometry, such as by tessellating or other procedural modification of source geometry, to produce final geometry on which a rendering will be based. An acceleration structure (or portion thereof) for use during ray tracing is defined based on the final geometry. Only coarse-grained elements of the acceleration structure may be produced or retained, and a fine-grained structure within a particular coarse-grained element may be Produced in response to a collection of rays being ready for traversal within the coarse grained element. Final geometry can be recreated in response to demand from a rasterization engine, and from ray intersection units that require such geometry for intersection testing with primitives. Geometry at different resolutions can be generated to respond to demands from different rendering components.
-
公开(公告)号：US20240371101A1
公开(公告)日：2024-11-07
申请号：US18776019
申请日：2024-07-17
Applicant: Imagination Technologies Limited
Inventor： John W. Howson
Abstract: Methods and tessellation modules for tessellating a patch to generate tessellated geometry data representing the tessellated patch. A plurality of tessellation pipelines operate in parallel as a core, configured to process a respective patch of a set of patches at a respective tessellation pipeline to identify tessellation factors for the patches of the set of patches. Tessellation instances to be used in tessellating the patches of the set are determined based on the identified tessellation factors for the patches of the set of patches. An allocation of the tessellation instances amongst the tessellation pipelines of the core is determined, and the tessellation instances allocated to the tessellation pipelines of the core at the allocated tessellation pipelines are processed to generate tessellated geometry data associated with the respective allocated tessellation instances.
-
公开(公告)号：US20240273804A1
公开(公告)日：2024-08-15
申请号：US18639733
申请日：2024-04-18
Applicant: Imagination Technologies Limited
Inventor： Panagiotis Velentzas , John W. Howson , Richard Broadhurst
CPC classification number: G06T15/005 , G06F9/5016
Abstract: A method of managing resources in a graphics processing pipeline includes, in response to selecting a task for execution within a texture/shading unit, allocating to the task both a static allocation of temporary registers for the entire task and a dynamic allocation of temporary registers. The dynamic allocation comprises temporary registers used by a first phase of the task only and the static allocation of temporary registers comprises any temporary registers that are used by the program and are live at a boundary between two phases. When the task subsequently reaches a boundary between two phases, the dynamic allocation of temporary registers are freed and a new dynamic allocation of temporary registers for a next phase of the task is allocated to the task.
-
Patent Agency Ranking
公开(公告)号：US12020362B2
公开(公告)日：2024-06-25
申请号：US18118262
申请日：2023-03-07
Applicant: Imagination Technologies Limited
Inventor： Diego Jesus , John W. Howson , Panagiotis Velentzas , Robert Brigg , Xile Yang
IPC: G06T15/00 , G06T1/20 , G06T1/60 , G06T9/00 , G06T11/20 , G06T11/40 , G06T15/04 , G06T17/10 , G06T17/20
CPC classification number: G06T15/005 , G06T1/20 , G06T1/60 , G06T9/00 , G06T11/20 , G06T11/40 , G06T15/00 , G06T15/04 , G06T17/10 , G06T17/20 , G06T2210/12
Abstract: Methods and control stream generators for generating a control stream for a tile group comprising at least two tiles, the control stream identifying primitive blocks that are relevant to rendering at least one tile in the tile group. Information is received identifying one or more primitive blocks relevant to rendering at least one tile in the tile group, each primitive block comprising one or more primitives; generating a primitive block entry for each of the identified primitive blocks; and adding each primitive block entry to the control stream; wherein generating the primitive block entry for at least one of the identified primitive blocks comprises: (i) identifying a bounding box encompassing the one or more primitives of the primitive block; (ii) generating a coverage mask that indicates which tiles of the tile group that intersect the bounding box for the primitive block are valid for the primitive block, a tile being valid for a primitive block if at least one primitive of the primitive blocks falls, at least partially, within the bounds of the tile; and (iii) including the coverage mask in the primitive block entry.
-
公开(公告)号：US11915363B2
公开(公告)日：2024-02-27
申请号：US18202933
申请日：2023-05-28
Applicant: Imagination Technologies Limited
Inventor： Robert Brigg , John W. Howson , Xile Yang
CPC classification number: G06T15/40 , G06T1/60 , G06T15/005
Abstract: A tag buffer implements a tag buffer stage of a rasterization phase in a tile-based rendering graphics processing system having a rendering space sub-divided into a plurality of tiles to which primitives can be associated. A buffer stores an identifier that identifies a visible primitive fragment at each sample position of a tile of the plurality of tiles. A look-up table stores an entry for transformed primitive blocks that indicates whether the tag buffer has received information identifying a primitive fragment associated with that transformed primitive block. The tag buffer receives information identifying primitive fragments that have survived a depth test, updates the buffer to indicate that an identified primitive fragment is the visible primitive fragment at the associated sample position, updates the look-up table to indicate which transformed primitive blocks the identified primitive fragments are associated with, and in response to flushing the contents of the buffer, compares the flushed contents of the buffer to the look-up table to thereby identify transformed primitive blocks that did not survive the tag buffer stage.
-
公开(公告)号：US20230385981A1
公开(公告)日：2023-11-30
申请号：US18231126
申请日：2023-08-07
Applicant: Imagination Technologies Limited
Inventor： Roger Hernando Buch , Panagiotis Velentzas , Richard Broadhurst , Xile Yang , John W. Howson
CPC classification number: G06T1/20 , G06F9/4881 , G06F9/5038 , G06F9/52 , G06F12/0261 , G06T1/60
Abstract: Methods and apparatus for merging tasks in a graphics pipeline in which, subsequent to a trigger to flush a tag buffer, one or more tasks from the flushed tag buffer are generated, each task comprising a reference to a program and plurality of fragments on which the program is to be executed, wherein a fragment is an element of a primitive at a sample position. It is then determined whether merging criteria are satisfied and if satisfied, one or more fragments from a next tag buffer flush are added to a last task of the one or more tasks generated from the flushed tag buffer.
-
公开(公告)号：US20230360306A1
公开(公告)日：2023-11-09
申请号：US18222968
申请日：2023-07-17
Applicant: Imagination Technologies Limited
Inventor： John W. Howson , Richard Broadhurst , Steven Fishwick
CPC classification number: G06T15/005 , G06T11/40 , G06T15/04 , G06T15/06 , G06T15/40 , G06T15/80 , G06T17/10 , G06F9/38 , G06T2200/28
Abstract: A graphics processing unit (GPU) processes graphics data using a rendering space which is sub-divided into a plurality of tiles. The GPU comprises cost indication logic configured to obtain a cost indication for each of a plurality of sets of one or more tiles of the rendering space. The cost indication for a set of tile(s) is suggestive of a cost of processing the set of one or more tiles. The GPU controls a rendering complexity with which primitives are rendered in tiles based on the cost indication for those tiles. This allows tiles to be rendered in a manner that is suitable based on the complexity of the graphics data within the tiles. In turn, this allows the rendering to satisfy constraints such as timing constraints even when the complexity of different tiles may vary significantly within an image.
-
公开(公告)号：US11798219B2
公开(公告)日：2023-10-24
申请号：US17903949
申请日：2022-09-06
Applicant: Imagination Technologies Limited
Inventor： John W. Howson
CPC classification number: G06T15/005 , G06F9/54 , G06T1/20 , G06T1/60 , G06T17/20
Abstract: A graphics processing engine has a geometry shading stage having two modes of operation. In the first mode of operation, each primitive output by the geometry shading stage is independent, whereas in the second mode of operation, connectivity between input primitives is maintained by the geometry shading stage. The mode of operation of the geometry shading stage can be determined based on the value of control state data which may be generated at compile-time for a geometry shader based on analysis of that geometry shader.
-
-
-
-
-
-
-
-
-
Search Results
204
records
(took 0.031 seconds)
