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    Apparatuses and methods for filtering noise from a video signal
    21.
    发明授权
    Apparatuses and methods for filtering noise from a video signal 有权

    公开(公告)号：US10609416B2

    公开(公告)日：2020-03-31

    申请号：US16032469

    申请日：2018-07-11

    Applicant: Integrated Device Technology, Inc.

    Inventor： Pavel Novotny

    IPC: H04N19/80 ,  H04N5/213 ,  H04N19/176 ,  H04N19/117 ,  H04N19/136 ,  G06T5/00 ,  H04N5/21

    Abstract: An apparatus includes a filter circuit and an encoder. The filter circuit may be configured to (i) calculate a noise level of a frame of a video signal based on a subset less than all of a plurality of blocks of the frame, where each of the blocks in the subset may have an associated weighted activity to variance ratio that exceeds a threshold value and (ii) generate a filtered video signal based on the noise level. An estimated noise level of each of the blocks in the subset may be selected from one of (a) an activity of the block, (b) another activity of a reference block of another frame and (c) a sum of absolute pixel differences between the block and the reference block. The encoder may be configured to generate a bitstream by encoding the filtered video signal.

    LOW POWER DELAY BUFFER BETWEEN EQUALIZER AND HIGH SENSITIVITY SLICER
    22.
    发明申请
    LOW POWER DELAY BUFFER BETWEEN EQUALIZER AND HIGH SENSITIVITY SLICER 审中-公开

    公开(公告)号：US20200075084A1

    公开(公告)日：2020-03-05

    申请号：US16565913

    申请日：2019-09-10

    Applicant: Integrated Device Technology, Inc.

    Inventor： David Chang

    IPC: G11C11/4093 ,  G11C11/4076

    Abstract: An apparatus includes a continuous-time linear equalizer circuit, a buffer and at least one slicer. The continuous-time linear equalizer circuit may be configured to generate a first intermediate signal by equalizing an input signal relative to a reference voltage. The input signal may be single-ended. The first intermediate signal may be differential. The buffer may be configured to generate a second intermediate signal by delaying the first intermediate signal. The second intermediate signal may be differential. The slicer may be configured to generate an output signal by slicing the second intermediate signal. The output signal may be single-ended.

    REAL-TIME AND ADAPTIVE RADIO-FREQUENCY POWER PROTECTION
    24.
    发明申请
    REAL-TIME AND ADAPTIVE RADIO-FREQUENCY POWER PROTECTION 审中-公开

    公开(公告)号：US20190356279A1

    公开(公告)日：2019-11-21

    申请号：US16226844

    申请日：2018-12-20

    Applicant: Integrated Device Technology, Inc.

    Inventor： Victor Korol ,  Roberto Aparicio Joo

    IPC: H03F1/54 ,  H03F1/04 ,  H03F3/189

    Abstract: An apparatus includes an amplifier circuit and a protection circuit. The amplifier circuit may be configured to generate an output signal by amplifying an input signal received at an input port. The input signal may be a radio-frequency signal. The protection circuit may be configured to (i) generate a detection signal by detecting when a level of the input signal exceeds a corresponding threshold, where the level is a power level, a voltage level or both, (ii) route the input signal away from the input port of the amplifier circuit and disable the amplifier circuit both in response to the detection signal being continuously active at least a first time duration and (iii) route the input signal to the input port of the amplifier circuit and enable the amplifier circuit both in response to the detection signal being continuously inactive at least a second time duration.

    DDR5 RCD INTERFACE PROTOCOL AND OPERATION
    25.
    发明申请
    DDR5 RCD INTERFACE PROTOCOL AND OPERATION 审中-公开

    公开(公告)号：US20190340141A1

    公开(公告)日：2019-11-07

    申请号：US15967823

    申请日：2018-05-01

    Applicant: Integrated Device Technology, Inc.

    Inventor： Shwetal Arvind Patel ,  Andy Zhang ,  Wen Jie Meng ,  Chenxiao Ren ,  Alejandro F. Gonzalez

    IPC: G06F13/16 ,  G06F3/06 ,  G06F1/10

    Abstract: An apparatus including a host interface and a registered clock driver interface. The host interface may be configured to receive an enable command from a host. The registered clock driver interface may be configured to perform power management for a dual in-line memory module, generate data for the dual in-line memory module, communicate the data, receive a clock signal and communicate an interrupt signal. The registered clock driver interface may be disabled at power on. The registered clock driver interface may be enabled by in response to the enable command. The apparatus may be implemented as a component on the dual in-line memory module.

    Open loop solution in data buffer and RCD
    26.
    发明授权
    Open loop solution in data buffer and RCD 有权

    公开(公告)号：US10437279B2

    公开(公告)日：2019-10-08

    申请号：US16194657

    申请日：2018-11-19

    Applicant: Integrated Device Technology, Inc.

    Inventor： David Chang ,  Xudong Shi

    IPC: G06F1/10 ,  H03K5/05 ,  G11C7/22 ,  H03L7/08 ,  G06F1/08 ,  G11C29/02 ,  G11C5/04 ,  G11C29/00 ,  G11C11/4096 ,  G11C11/4076 ,  G11C7/10

    Abstract: An apparatus includes a clock tree circuit, a first phase interpolator circuit and a second phase interpolator circuit. The clock tree circuit may be configured to generate a first clock delayed from a system clock by a constant time. The first phase interpolator circuit may be in a calibration loop and configured to generate a second clock with a programmable phase delay relative to the first clock. The programmable phase delay may be controlled by a control value. The calibration loop may be configured to determine the control value that results in a given delay between the system clock and the second clock. The second phase interpolator circuit may be in a normal signal path and configured to generate a third clock with the given delay relative to the first clock using the control value such that the third clock is offset from the system clock by the given delay.

    LOWER POWER AUTO-ZEROING RECEIVER INCORPORATING CTLE, VGA, AND DFE
    27.
    发明申请
    LOWER POWER AUTO-ZEROING RECEIVER INCORPORATING CTLE, VGA, AND DFE 审中-公开

    公开(公告)号：US20190296691A1

    公开(公告)日：2019-09-26

    申请号：US16357609

    申请日：2019-03-19

    Applicant: Integrated Device Technology, Inc.

    Inventor： Steven E. Finn

    IPC: H03D3/00 ,  H03G3/30 ,  H03K5/1536 ,  H04L27/156 ,  H04L25/06 ,  H04L25/03 ,  H03G1/00 ,  H03G1/04 ,  H04L1/20 ,  G11C7/10 ,  G11C7/22

    Abstract: An apparatus includes a first half-cell, a second half cell and a multiplexer. The first half-cell may comprise a first input stage configured to present a first input signal to a first auto-zero stage. The second half-cell may comprise a second input stage configured to present a second input signal to a second auto-zero stage. The multiplexer may receive a first output from the first auto-zero stage, receive a second output from the second auto-zero stage and present one of the first output and the second output. The first half-cell and the second half-cell may implement a capacitive coupling. The capacitive coupling may provide a rail-to-rail common-mode input range. The first half-cell and the second half-cell may prevent a mismatch between data signals and clock signals. The first half-cell and the second half-cell may each be configured to implement a calibration when idle.

    Register clock driver for DDR5 memory
    28.
    发明授权
    Register clock driver for DDR5 memory 有权

    公开(公告)号：US10401899B2

    公开(公告)日：2019-09-03

    申请号：US15605408

    申请日：2017-05-25

    Applicant: Integrated Device Technology, Inc.

    Inventor： Shwetal Arvind Patel

    IPC: G06F13/16 ,  G06F1/10

    Abstract: A register clock driver for a DDR5 memory is presented. A register clock driver (RCD) can include a logic having one or more input channels, each of the one or more input channels receiving input signals; and a plurality of ranked output ports associated with each of the one or more input channels, the logic providing the input signals received on each of the one or more input channels to the associated plurality of ranked output ports according to control signals. The RCD can operate in a default mode, wherein input signals from the input channels are output to both of the output ports associated with that channel, or can operate in a non-default mode where input signals from the input channels are sent to the appropriate ranked output port associated with that channel. In either case, unused signaling on the output ports is held high.

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