公开(公告)号：US11887863B2

公开(公告)日：2024-01-30

申请号：US17447029

申请日：2021-09-07

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： HunTeak Lee ,  Gwang Kim ,  Junho Ye

IPC: H01L21/48 ,  H01L21/56 ,  H01L23/60 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L23/498 ,  H01L23/31

CPC classification number: H01L21/4853 ,  H01L21/561 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/49811 ,  H01L23/60 ,  H01L24/81 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/81815 ,  H01L2924/1532

Abstract: A semiconductor device has a substrate and a first component disposed over a first surface of the substrate. A connector is disposed over the first surface of the substrate. A first encapsulant is deposited over the first component while the connector remains outside of the first encapsulant. A shielding layer is formed over the first encapsulant while the connector remains outside of the shielding layer. A second component is disposed over a second surface of the substrate. A solder bump is disposed over the second surface of the substrate. A second encapsulant is deposited over the second surface of the substrate. An opening is formed through the second encapsulant to expose the solder bump. A solder ball is disposed in the opening. The solder ball and solder bump are reflowed to form a combined solder bump.

公开(公告)号：US20240021566A1

公开(公告)日：2024-01-18

申请号：US17812836

申请日：2022-07-15

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： WooSoon Kim ,  JoonYoung Choi ,  YoungCheol Kim ,  KyungOe Kim

IPC: H01L23/00 ,  H01L25/16 ,  H01L21/56

CPC classification number: H01L24/32 ,  H01L24/94 ,  H01L24/97 ,  H01L24/16 ,  H01L24/73 ,  H01L25/167 ,  H01L24/27 ,  H01L21/563 ,  H01L2924/12043 ,  H01L2924/13056 ,  H01L2924/15311 ,  H01L2924/182 ,  G02B6/13

Abstract: A semiconductor device has a semiconductor die with a sensitive area. A dam wall is formed over the semiconductor die proximate to the sensitive area. In one embodiment, the dam wall has a vertical segment and side wings. The dam wall can have a plurality of rounded segments integrated with a plurality of vertical segments as a unitary body. Alternatively, the dam wall has a plurality of separate vertical segments arranged in two or more overlapping rows. A plurality of conductive posts is formed over the semiconductor die. An electrical component is disposed over the semiconductor die. The semiconductor die and electrical component are disposed over a substrate. An insulating layer is formed over the substrate outside the dam wall. An underfill material is deposited between the semiconductor die and substrate. The dam wall and insulating layer inhibit the underfill material from contacting any portion of the sensitive area.

公开(公告)号：US20240021490A1

公开(公告)日：2024-01-18

申请号：US17812224

申请日：2022-07-13

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Jongtae Kim

IPC: H01L23/367 ,  H01L25/16 ,  H01L23/552 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L23/3675 ,  H01L25/165 ,  H01L25/162 ,  H01L23/552 ,  H01L21/4882 ,  H01L23/49816 ,  H01L24/16

Abstract: A semiconductor device has a substrate and a semiconductor package disposed over the substrate. An embedded bar (e-bar) substrate is disposed on the substrate around the semiconductor package. A heat sink is formed over the semiconductor package and supported by the e-bar substrate to elevate the heat sink from the substrate and reduce a thickness of the heat sink. A thermal interface material is deposited between the semiconductor package and heat sink. Alternatively, a shield layer can be formed over the semiconductor package and supported by the e-bar substrate. The e-bar substrate has a base layer and a first metal layer formed over a first surface of the base layer. A bump is formed over the first metal layer. A second metal layer can be over a second surface of the base layer opposite the first surface of the base layer. Two or more e-bar substrates can be stacked.

公开(公告)号：US20230411831A1

公开(公告)日：2023-12-21

申请号：US18334375

申请日：2023-06-14

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： HunTeak LEE ,  SangHo SONG ,  YeonJee LEE

IPC: H01Q1/24 ,  H01L23/66 ,  H01L23/64 ,  H01L23/498

CPC classification number: H01Q1/243 ,  H01L23/66 ,  H01L23/645 ,  H01L23/49816 ,  H01L2223/6677

Abstract: An antenna module comprises: an antenna body comprising a first surface for attaching the antenna module to an external substrate, and a second surface through which the antenna module transmits and receives electromagnetic signals, wherein the first surface is opposite to the second surface; an antenna conductive pattern formed within the antenna body; and a shielding fence laterally surrounding the antenna conductive pattern for shielding electromagnetic interferences.

公开(公告)号：US20230411346A1

公开(公告)日：2023-12-21

申请号：US18332023

申请日：2023-06-09

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： JoonYoung CHOI ,  WooSoon KIM ,  SeongKwon HONG ,  GaYeon KIM

IPC: H01L23/00 ,  H01L23/373 ,  H01L23/367 ,  H01L21/48

CPC classification number: H01L24/81 ,  H01L2224/81986 ,  H01L23/3675 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L21/4882 ,  H01L2224/81224 ,  H01L2224/81815 ,  H01L2224/73204 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2924/35121 ,  H01L2924/1616 ,  H01L2924/16251 ,  H01L2924/1632 ,  H01L23/3736

Abstract: A semiconductor device and a method for forming the same are provided. The method includes: providing a substrate; providing a semiconductor die having a first die surface and a second die surface opposite to the first die surface; attaching the first die surface to the substrate via an interconnect structure comprising solder; and irradiating the second die surface with a laser beam, wherein the laser beam passes through the semiconductor die and reflows the solder of the interconnect structure. In the method, laser-assisted bonding can is used to reflow solder bumps, and thermal interface material can be formed after the laser-assisted bonding.

公开(公告)号：US20230411305A1

公开(公告)日：2023-12-21

申请号：US18315479

申请日：2023-05-10

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： SeongHwan PARK ,  Bom LEE ,  KyoungHee PARK

IPC: H01L23/552 ,  H01L23/31 ,  H01L25/065 ,  H01L21/56

CPC classification number: H01L23/552 ,  H01L23/3121 ,  H01L2225/06537 ,  H01L21/56 ,  H01L25/0657

Abstract: A method for selectively forming a shielding layer on a semiconductor device comprises: attaching a tape stack onto a predetermined area of a substrate of the semiconductor device, wherein the tape stack comprises a lower tape layer that covers the predetermined area and an upper tape layer that extends beyond the predetermined area and overhangs above an intermediate area adjacent to the predetermined area; applying a shielding layer to the substrate of the semiconductor device; and removing the tape stack and a portion of the shielding layer formed on the tape stack from the substrate of the semiconductor device.

公开(公告)号：US20230402401A1

公开(公告)日：2023-12-14

申请号：US18455419

申请日：2023-08-24

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： ChangOh Kim ,  KyoWang Koo ,  SungWon Cho ,  BongWoo Choi ,  JiWon Lee

IPC: H01L23/552 ,  H01L21/311 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00 ,  H01L23/66

CPC classification number: H01L23/552 ,  H01L21/31144 ,  H01L21/565 ,  H01L23/3128 ,  H01L24/09 ,  H01L24/17 ,  H01L23/66 ,  H01L21/563

Abstract: A semiconductor device has a substrate. An electrical component is disposed over a surface of the substrate. An encapsulant is deposited over the electrical component and substrate. A portion of the surface of the substrate remains exposed from the encapsulant. A shielding layer is formed over the encapsulant. A portion of the shielding layer is removed to expose the portion of the surface of the substrate.

公开(公告)号：US20230395477A1

公开(公告)日：2023-12-07

申请号：US17805096

申请日：2022-06-02

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： GunHyuck Lee ,  HeeSoo Lee ,  SangHyun Son ,  Bokyeong Hwang

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/552 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/49805 ,  H01L23/3121 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/552 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565

Abstract: A semiconductor device has an interconnect substrate with a conductive via. A first electrical component is disposed over a major surface of the interconnect substrate. An electrical interconnect compound is disposed over the conductive via exposed from a side surface of the interconnect substrate. The electrical interconnect compound can be applied with a tilt nozzle oriented at an angle. A second electrical component is disposed on the electrical interconnect compound on the conductive via exposed from the side surface of the interconnect substrate. A plurality of second electrical components can be disposed on two or more side surfaces of the interconnect substrate. The interconnect substrate can have a plurality of stacked conductive vias and the second electrical component is disposed over the stacked conductive vias. An encapsulant is deposited over the first electrical component and interconnect substrate. A shielding layer can be formed over the encapsulant.

公开(公告)号：US20230361103A1

公开(公告)日：2023-11-09

申请号：US18355906

申请日：2023-07-20

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： ChangOh Kim ,  JinHee Jung

IPC: H01L25/00 ,  H01L21/78 ,  H01L21/56 ,  H01L25/065 ,  H01L23/552

CPC classification number: H01L25/50 ,  H01L21/78 ,  H01L21/56 ,  H01L25/0652 ,  H01L23/552 ,  H01L2225/06524

Abstract: A semiconductor device is formed by providing a semiconductor package including a shielding layer and forming a slot in the shielding layer using a laser. The laser is turned on and exposed to the shielding layer with a center of the laser disposed over a first point of the shielding layer. The laser is moved in a loop while the laser remains on and exposed to the shielding layer. Exposure of the laser to the shielding layer is stopped when the center of the laser is disposed over a second point of the shielding layer. A distance between the first point and the second point is approximately equal to a radius of the laser.

公开(公告)号：US20230343732A1

公开(公告)日：2023-10-26

申请号：US18343606

申请日：2023-06-28

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： HunTeak Lee ,  Choon Heung Lee ,  JunHo Ye

IPC: H01L23/66 ,  H01L23/31 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01Q1/22 ,  H01L23/552

CPC classification number: H01L23/66 ,  H01L23/3121 ,  H01L23/5386 ,  H01L21/4853 ,  H01L21/565 ,  H01Q1/2283 ,  H01L23/552 ,  H01L2223/6677

Abstract: A semiconductor device has an electrical component assembly, and a plurality of discrete antenna modules disposed over the electrical component assembly. Each discrete antenna module is capable of providing RF communication for the electrical component assembly. RF communication can be enabled for a first one of the discrete antenna modules, while RF communication is disabled for a second one of the discrete antenna modules. Alternatively, RF communication is enabled for the second one of the discrete antenna modules, while RF communication is disabled for the first one of the discrete antenna modules. A bump is formed over the discrete antenna modules. An encapsulant is deposited around the discrete antenna modules. A shielding layer is formed over the electrical components assembly. A stud or core ball can be formed internal to a bump connecting the discrete antenna modules to the electrical component assembly.