-
公开(公告)号：US20230005744A1
公开(公告)日：2023-01-05
申请号：US17850370
申请日：2022-06-27
Applicant: ASM IP Holding B.V.
Inventor： Caleb Miskin , Omar Elleuch , Peter Westrom , Rami Khazaka , Qi Xie , Alexandros Demos
IPC: H01L21/02 , C23C16/455
Abstract: A method of forming a structure includes supporting a substrate within a reaction chamber of a semiconductor processing system, the substrate having a recess with a bottom surface and a sidewall surface extending upwards from the bottom surface of the recess. A film is deposited within the recess and onto the bottom surface and the sidewall surface of the recess, the film having a bottom segment overlaying the bottom surface of the recess and a sidewall segment deposited onto the sidewall surface of the recess. The sidewall segment of the film is removed while at least a portion bottom segment of the film is retained within the recess, the sidewall segment of the film removed from the sidewall surface more rapidly than removing the bottom segment of the film from the bottom surface of the recess. Semiconductor processing systems and structures formed using the method are also described.
-
公开(公告)号：US11495459B2
公开(公告)日：2022-11-08
申请号：US16998220
申请日：2020-08-20
Applicant: ASM IP Holding B.V.
Inventor： Lucas Petersen Barbosa Lima , Rami Khazaka , Qi Xie
IPC: H01L21/02 , H01L29/167 , H01L21/311
Abstract: Methods and systems for selectively depositing a p-type doped silicon germanium layer and structures and devices including a p-type doped silicon germanium layer are disclosed. An exemplary method includes providing a substrate, comprising a surface comprising a first area comprising a first material and a second area comprising a second material, within a reaction chamber; depositing a p-type doped silicon germanium layer overlying the surface, the p-type doped silicon germanium layer comprising gallium; and depositing a cap layer overlying the p-type doped silicon germanium layer. The method can further include an etch step to remove the cap layer and the p-type doped silicon germanium layer overlying the second material.
-
公开(公告)号：US20210391172A1
公开(公告)日：2021-12-16
申请号：US17345458
申请日：2021-06-11
Applicant: ASM IP Holding B.V.
Inventor： Lucas Petersen Barbosa Lima , Rami Khazaka , Qi Xie
Abstract: Methods and devices for epitaxially growing boron doped silicon germanium layers. The layers may be used, for example, as a p-type source and/or drain regions in field effect transistors.
-
公开(公告)号：US20210118679A1
公开(公告)日：2021-04-22
申请号：US17064041
申请日：2020-10-06
Applicant: ASM IP Holding B.V.
Inventor： Lucas Petersen Barbosa Lima , Rami Khazaka , Qi Xie
IPC: H01L21/02 , H01L29/08 , C23C16/455
Abstract: Methods and systems for selectively depositing material, such as doped semiconductor material, are disclosed. An exemplary method includes providing a substrate, comprising a first area comprising a first material and a second area comprising a second material, selectively depositing a first doped semiconductor layer overlying the first material relative to the second material and selectively depositing a second doped semiconductor layer overlying the first doped semiconductor layer relative to the second material.
-
公开(公告)号：US20250157814A1
公开(公告)日：2025-05-15
申请号：US19021548
申请日：2025-01-15
Applicant: ASM IP Holding B.V.
Inventor： Lucas Petersen Barbosa Lima , Rami Khazaka , Qi Xie
Abstract: Methods and devices for epitaxially growing boron doped silicon germanium layers. The layers may be used, for example, as a p-type source and/or drain regions in field effect transistors.
-
Patent Agency Ranking
公开(公告)号：US12266695B2
公开(公告)日：2025-04-01
申请号：US18107688
申请日：2023-02-09
Applicant: ASM IP Holding B.V.
Inventor： Lucas Petersen Barbosa Lima , Rami Khazaka , Qi Xie
IPC: H01L29/167 , H01L21/02 , H01L21/67
Abstract: Methods and systems for depositing material, such as doped semiconductor material, are disclosed. An exemplary method includes providing a substrate, forming a first doped semiconductor layer overlying the substrate, and forming a second doped semiconductor layer overlying the first doped semiconductor layer, wherein the first doped semiconductor layer comprises a first dopant and a second dopant, and wherein the second doped semiconductor layer comprises the first dopant. Structures and devices formed using the methods and systems for performing the methods are also disclosed.
-
公开(公告)号：US20240203730A1
公开(公告)日：2024-06-20
申请号：US18544019
申请日：2023-12-18
Applicant: ASM IP Holding B.V.
Inventor： Rami Khazaka , Patricio Romero , Michael Eugene Givens , Charles Dezelah
CPC classification number: H01L21/02532 , C30B25/16 , C30B25/20 , C30B29/52 , C30B31/08 , C30B33/12 , H01L21/02576 , H01L21/02579 , H01L21/02609 , H01L21/02636
Abstract: A method of forming a Si-comprising epitaxial layer selectively on a substrate and a semiconductor processing apparatus is disclosed. Embodiments of the presently described method of forming the Si-comprising epitaxial layer comprise performing a deposition process for forming the Si-comprising epitaxial layer selectively on a first exposed single crystalline surface relative to a second exposed single crystalline surface being different than the first exposed single crystalline surface.
-
28.发明公开公开(公告)号：US20240026567A1
公开(公告)日：2024-01-25
申请号：US18350517
申请日：2023-07-11
Applicant: ASM IP Holding, B.V.
Inventor： Rami Khazaka
CPC classification number: C30B25/165 , H01L21/0245 , H01L21/02532 , H01L21/02576 , H01L21/0262 , C23C16/45529 , C23C16/45546 , C23C16/52 , C23C16/24 , C30B25/12 , C30B29/06 , C30B29/68 , H10B12/01
Abstract: A method for forming an epitaxial stack on a plurality of substrates comprises providing a plurality of substrates to a process chamber and executing deposition cycles, wherein each deposition cycle comprises a first deposition pulse and a second deposition pulse. The epitaxial stack comprises a first epitaxial layer stacked alternatingly and repeatedly with a second epitaxial layer, the second epitaxial layer being different from the first epitaxial layer. The first deposition pulse comprises a provision of a first reaction gas mixture to the process chamber, thereby forming the first epitaxial layer having a first native lattice parameter. The second deposition pulse comprises a provision of a second reaction gas mixture to the process chamber, thereby forming the second epitaxial layer having a second native lattice parameter, wherein the first native lattice parameter lies in a range within 1.5% larger than and 0.9% smaller than the second native lattice parameter.
-
29.发明公开公开(公告)号：US20230349069A1
公开(公告)日：2023-11-02
申请号：US18307447
申请日：2023-04-26
Applicant: ASM IP Holding, B.V.
Inventor： Wonjong Kim , Rami Khazaka , Michael Givens , Charles Dezelah
CPC classification number: C30B25/165 , C30B29/52 , C30B31/08 , C30B31/18 , C30B33/08
Abstract: Some examples herein provide a method of forming a doped silicon germanium layer. The method may include simultaneously exposing a substrate to (a) a silicon precursor, (b), a germanium precursor, (c) a boron precursor, and (d) a heteroleptic gallium precursor. The heteroleptic gallium precursor may include (i) at least one straight chain alkyl group in which a terminal carbon is directly bonded to gallium, and (ii) at least one tertiary alkyl group in which a tertiary carbon is directly bonded to gallium. The method may include reacting the silicon precursor, the germanium precursor, the boron precursor, and the heteroleptic gallium precursor to form a silicon germanium layer on the substrate that is doped with boron and gallium.
-
公开(公告)号：US11781243B2
公开(公告)日：2023-10-10
申请号：US17166160
申请日：2021-02-03
Applicant: ASM IP Holding B.V.
Inventor： Rami Khazaka , Lucas Petersen Barbosa Lima , Qi Xie
CPC classification number: C30B29/06 , C30B23/005 , C30B23/025 , C30B31/10 , C30B31/18
Abstract: Methods and devices for low-temperature deposition of phosphorous-doped silicon layers. Disilane is used as a silicon precursor, and nitrogen or a noble gas is used as a carrier gas. Phosphine is a suitable phosphorous precursor.
-
-
-
-
-
-
-
-
-
Search Results
34
records
(took 0.034 seconds)
