公开(公告)号：US20210192827A1

公开(公告)日：2021-06-24

申请号：US16723969

申请日：2019-12-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Skyler Jonathon Saleh ,  Vineet Goel ,  Pazhani Pillai ,  Ruijin Wu ,  Christopher J. Brennan ,  Andrew S. Pomianowski

IPC: G06T15/00 ,  G06T1/60 ,  G06T1/20

Abstract: Techniques for performing shader operations are provided. The techniques include, performing pixel shading at a shading rate defined by pixel shader variable rate shading (“VRS”) data, updating the pixel VRS data that indicates one or more shading rates for one or more tiles based on whether the tiles of the one or more tiles include triangle edges or do not include triangle edges, to generate updated VRS data, and writing a VRS rate feedback buffer based on the updated VRS data.

公开(公告)号：US11967043B2

公开(公告)日：2024-04-23

申请号：US18089209

申请日：2022-12-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Alexander M. Potapov ,  Skyler Jonathon Saleh ,  Swapnil P. Sakharshete ,  Vineet Goel

IPC: G06T3/40 ,  G06T3/4046 ,  G06T3/4053 ,  G06T3/4069

CPC classification number: G06T3/4046 ,  G06T3/4053 ,  G06T3/4069

Abstract: A processing device is provided which includes memory and a processor. The processor is configured to receive an input image having a first resolution, generate at least one linear down-sampled version of the input image via a linear upscaling network, generate at least one non-linear down-sampled version of the input image via a non-linear upscaling network, extract a first feature map from the at least one linear down-sampled version of the input image, and extract a second feature map from the at least one non-linear down-sampled version of the input image. The processor is also configured to convert the at least one linear down-sampled version of the input image and the at least one non-linear down-sampled version of the input image into pixels of an output image having a second resolution higher than the first resolution using the first feature map and the second feature map.

公开(公告)号：US20230140100A1

公开(公告)日：2023-05-04

申请号：US18089209

申请日：2022-12-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Alexander M. Potapov ,  Skyler Jonathon Saleh ,  Swapnil P. Sakharshete ,  Vineet Goel

IPC: G06T3/40

Abstract: A processing device is provided which includes memory and a processor. The processor is configured to receive an input image having a first resolution, generate at least one linear down-sampled version of the input image via a linear upscaling network, generate at least one non-linear down-sampled version of the input image via a non-linear upscaling network, extract a first feature map from the at least one linear down-sampled version of the input image, and extract a second feature map from the at least one non-linear down-sampled version of the input image. The processor is also configured to convert the at least one linear down-sampled version of the input image and the at least one non-linear down-sampled version of the input image into pixels of an output image having a second resolution higher than the first resolution using the first feature map and the second feature map.

公开(公告)号：US20220198739A1

公开(公告)日：2022-06-23

申请号：US17129766

申请日：2020-12-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Skyler Jonathon Saleh ,  Maxim V. Kazakov ,  Swapnil P. Sakharshete ,  Takahiro Harada ,  Vineet Goel

IPC: G06T15/06 ,  G06T15/00

Abstract: A technique for performing ray tracing operations is provided. The technique includes performing bounding volume hierarchy (“BVH”) traversal in multiple accelerated processing devices (“APDs”), utilizing bounding volume hierarchy data copies in memories local to the multiple APDs; rendering primitives determined to be intersected based on the BVH traversal, using geometry information and texture data spread across the memories local to the multiple APDs; and storing results of rendered primitives for a set of tiles assigned to the multiple APDs into tile buffers stored in APD memories local to the APDs.

公开(公告)号：US20210026686A1

公开(公告)日：2021-01-28

申请号：US16933863

申请日：2020-07-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Swapnil P. Sakharshete ,  Andrew S. Pomianowski ,  Maxim V. Kazakov ,  Vineet Goel ,  Milind N. Nemlekar ,  Skyler Jonathon Saleh

IPC: G06F9/48 ,  G06F9/38 ,  G06F9/30 ,  G06F12/0893 ,  G06F12/128 ,  G06N20/00 ,  G06F13/28

Abstract: Techniques for performing machine learning operations are provided. The techniques include configuring a first portion of a first chiplet as a cache; performing caching operations via the first portion; configuring at least a first sub-portion of the first portion of the chiplet as directly-accessible memory; and performing machine learning operations with the first sub-portion by a machine learning accelerator within the first chiplet.

公开(公告)号：US20200184002A1

公开(公告)日：2020-06-11

申请号：US16557911

申请日：2019-08-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Swapnil P. Sakharshete ,  Samuel Lawrence Wasmundt ,  Maxim V. Kazakov ,  Vineet Goel

IPC: G06F17/16 ,  G06N3/08

Abstract: A processing device is provided which includes memory configured to store data and a processor configured to determine, based on convolutional parameters associated with an image, a virtual general matrix-matrix multiplication (GEMM) space of a virtual GEMM space output matrix and generate, in the virtual GEMM space output matrix, a convolution result by matrix multiplying the data corresponding to a virtual GEMM space input matrix with the data corresponding to a virtual GEMM space filter matrix. The processing device also includes convolutional mapping hardware configured to map, based on the convolutional parameters, positions of the virtual GEMM space input matrix to positions of an image space of the image.

公开(公告)号：US10453243B2

公开(公告)日：2019-10-22

申请号：US16238727

申请日：2019-01-03

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Anirudh R. Acharya ,  Swapnil Sakharshete ,  Michael Mantor ,  Mangesh P. Nijasure ,  Todd Martin ,  Vineet Goel

IPC: G06T15/00 ,  G06T1/20 ,  G06T15/80 ,  G06F9/50 ,  G06F9/48

Abstract: Processing of non-real-time and real-time workloads is performed using discrete pipelines. A first pipeline includes a first shader and one or more fixed function hardware blocks. A second pipeline includes a second shader that is configured to emulate the at least one fixed function hardware block. First and second memory elements store first state information for the first pipeline and second state information for the second pipeline, respectively. A non-real-time workload executing in the first pipeline is preempted at a primitive boundary in response to a real-time workload being dispatched for execution in the second pipeline. The first memory element retains the first state information in response to preemption of the non-real-time workload. The first pipeline is configured to resume processing the subsequent primitive on the basis of the first state information stored in the first memory element.

公开(公告)号：US20190172173A1

公开(公告)日：2019-06-06

申请号：US15832131

申请日：2017-12-05

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Usame Ceylan ,  Young In Yeo ,  Todd Martin ,  Vineet Goel

IPC: G06T1/20 ,  G06T11/00 ,  G06T15/00

Abstract: A compute unit accesses a chunk of bits that represent indices of vertices of a graphics primitive. The compute unit sets values of a first bit to indicate whether the chunk is monotonic or ordinary, second bits to define an offset that is determined based on values of indices in the chunk, and sets of third bits that determine values of the indices in the chunk based on the offset defined by the second bits. The compute unit writes a compressed chunk represented by the first bit, the second bits, and the sets of third bits to a memory. The compressed chunk is decompressed and the decompressed indices are written to an index buffer. In some embodiments, the indices are decompressed based on metadata that includes offsets that are determined based on values of the indices and bitfields that indicate characteristics of the indices.