公开(公告)号：US10332612B2

公开(公告)日：2019-06-25

申请号：US15878284

申请日：2018-01-23

Applicant: Altera Corporation

Inventor： Ryan Fung ,  Valavan Manohararajah

IPC: G11C7/00 ,  G11C29/02 ,  H03K5/131 ,  H03K19/177 ,  G11C29/50

Abstract: Integrated circuits with memory interface circuitry may be provided. Prior to calibration, a number of samples may be determined by computing probability density function curves as a function of timing window edge asymmetry for different degrees of oversampling. During calibration, duty cycle distortion in data strobe signals may be corrected by selectively delaying the data strobe rising or falling edges. A data clock signal that is used for generating data signals may also suffer from duty cycle distortion. The rising and falling edges of the data clock signal may be selectively delayed to correct for duty cycle distortion. The data path through which the data signals are routed may be adjusted to equalize rising and falling transitions to minimize data path duty cycle distortion. Multi-rank calibration may be performed by calibrating to an intersection of successful settings that allow each memory rank to pass memory operation tests.

公开(公告)号：US09911506B1

公开(公告)日：2018-03-06

申请号：US15416347

申请日：2017-01-26

Applicant: Altera Corporation

Inventor： Ryan Fung ,  Valavan Manohararajah

IPC: G11C7/00 ,  G11C29/02

CPC classification number: G11C29/022 ,  G11C29/023 ,  G11C29/50012 ,  H03K5/131 ,  H03K19/17744

Abstract: Integrated circuits with memory interface circuitry may be provided. Prior to calibration, a number of samples may be determined by computing probability density function curves as a function of timing window edge asymmetry for different degrees of oversampling. During calibration, duty cycle distortion in data strobe signals may be corrected by selectively delaying the data strobe rising or falling edges. A data clock signal that is used for generating data signals may also suffer from duty cycle distortion. The rising and falling edges of the data clock signal may be selectively delayed to correct for duty cycle distortion. The data path through which the data signals are routed may be adjusted to equalize rising and falling transitions to minimize data path duty cycle distortion. Multi-rank calibration may be performed by calibrating to an intersection of successful settings that allow each memory rank to pass memory operation tests.

公开(公告)号：US09401718B1

公开(公告)日：2016-07-26

申请号：US14681419

申请日：2015-04-08

Applicant: Altera Corporation

Inventor： David Lewis ,  Valavan Manohararajah ,  David Galloway

IPC: H03K19/177

CPC classification number: H03K19/177 ,  G06F17/5054 ,  H01L25/00 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of configuring a programmable integrated circuit device with a user logic design includes analyzing the user logic design to identify unidirectional logic paths within the user logic design and cyclic logic paths within the user logic design, assigning the cyclic logic paths to logic in a first portion of the programmable integrated circuit device that operates at a first data rate, assigning the unidirectional logic paths to logic in a second portion of the programmable integrated circuit device that operates at a second data rate lower than the first data rate, and pipelining the unidirectional data paths in the second portion of the programmable integrated circuit device to compensate for the lower second data rate. A programmable integrated circuit device adapted to carry out such method may have logic regions operating at different rates, including logic regions with programmably selectable data rates.

公开(公告)号：US20150033198A1

公开(公告)日：2015-01-29

申请号：US14484655

申请日：2014-09-12

Applicant: Altera Corporation

Inventor： Ryan Fung ,  David Lewis ,  Valavan Manohararajah

IPC: G06F17/50

CPC classification number: G06F17/5054 ,  G06F17/50 ,  G06F17/5045 ,  G06F17/5059 ,  G06F17/5077 ,  G06F2217/84 ,  H03K19/17728 ,  H03K19/17736

Abstract: A method of configuring an integrated circuit device with a user logic design includes analyzing the user logic design to identify timing requirements of paths within the user logic design, determining latency requirements along those paths, routing the user logic design based on availability of storage elements for incorporation into those paths to satisfy the latency requirements, and retiming the user logic design following that routing by incorporating at least some of the storage elements.

Abstract translation: 配置具有用户逻辑设计的集成电路设备的方法包括分析用户逻辑设计以识别用户逻辑设计内的路径的定时要求，确定沿着这些路径的等待时间要求，基于存储元件的可用性路由用户逻辑设计， 并入到这些路径中以满足等待时间要求，并且通过并入至少一些存储元件来重新定时跟踪该路由之后的用户逻辑设计。

公开(公告)号：US20210082534A1

公开(公告)日：2021-03-18

申请号：US17093292

申请日：2020-11-09

Applicant: Altera Corporation

Inventor： Ryan Fung ,  Valavan Manohararajah

IPC: G11C29/02 ,  H03K5/131 ,  H03K19/17736 ,  G11C29/50

Abstract: Integrated circuits with memory interface circuitry may be provided. Prior to calibration, a number of samples may be determined by computing probability density function curves as a function of timing window edge asymmetry for different degrees of oversampling. During calibration, duty cycle distortion in data strobe signals may be corrected by selectively delaying the data strobe rising or falling edges. A data clock signal that is used for generating data signals may also suffer from duty cycle distortion. The rising and falling edges of the data clock signal may be selectively delayed to correct for duty cycle distortion. The data path through which the data signals are routed may be adjusted to equalize rising and falling transitions to minimize data path duty cycle distortion. Multi-rank calibration may be performed by calibrating to an intersection of successful settings that allow each memory rank to pass memory operation tests.

公开(公告)号：US10019234B2

公开(公告)日：2018-07-10

申请号：US14875323

申请日：2015-10-05

Applicant: Altera Corporation

Inventor： Valavan Manohararajah

IPC: G06F7/544

CPC classification number: G06F7/5443 ,  G06F2207/3868

Abstract: An integrated circuit may have specialized processing blocks that are configurable to operate as arithmetic operators that may implement, amongst other functions, multiplication and multiply-accumulation operations in a first mode. In a second mode, a sequencer circuit may provide data signals and control signals to the specialized processing blocks such that the specialized processing block operates as a signal processing device that handles signals in a given sequence. For example, the sequencer circuit may control the signal arrival at the specialized processing block and the configuration of the configurable circuitry in the specialized processing block. In certain embodiments, the sequencer circuit and the specialized processing block may implement finite impulse response (FIR) filters.

公开(公告)号：US20180151243A1

公开(公告)日：2018-05-31

申请号：US15878284

申请日：2018-01-23

Applicant: Altera Corporation

Inventor： Ryan Fung ,  Valavan Manohararajah

IPC: G11C29/02

CPC classification number: G11C29/022 ,  G11C29/023 ,  G11C29/50012 ,  H03K5/131 ,  H03K19/17744

Abstract: Integrated circuits with memory interface circuitry may be provided. Prior to calibration, a number of samples may be determined by computing probability density function curves as a function of timing window edge asymmetry for different degrees of oversampling. During calibration, duty cycle distortion in data strobe signals may be corrected by selectively delaying the data strobe rising or falling edges. A data clock signal that is used for generating data signals may also suffer from duty cycle distortion. The rising and falling edges of the data clock signal may be selectively delayed to correct for duty cycle distortion. The data path through which the data signals are routed may be adjusted to equalize rising and falling transitions to minimize data path duty cycle distortion. Multi-rank calibration may be performed by calibrating to an intersection of successful settings that allow each memory rank to pass memory operation tests.

公开(公告)号：US09553590B1

公开(公告)日：2017-01-24

申请号：US13662795

申请日：2012-10-29

Applicant: Altera Corporation

Inventor： Valavan Manohararajah ,  David Lewis

IPC: H03K19/177 ,  H03K19/173 ,  G06F9/30 ,  G06F7/57 ,  G06F7/38 ,  G06F17/30 ,  G06F17/50

CPC classification number: H03K19/17708 ,  G06F9/30 ,  G06F17/30221 ,  G06F17/5027 ,  G06F17/5054 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736

Abstract: A programmable integrated circuit device includes a plurality of clusters of programmable logic resources. Programmable device interconnect resources allow user-defined interconnection between the clusters of programmable logic resources. A plurality of specialized processing blocks have dedicated arithmetic operators and programmable internal interconnect resources, and having inputs and outputs programmably connectable to the programmable device interconnect resources. A plurality of dedicated memory modules have inputs and outputs programmably connectable to the programmable device interconnect resources. Programmably connectable direct interconnect between at least one respective individual one of the specialized processing blocks and at least one respective individual one of the dedicated memory modules allow the formation of a processor element from a specialized processing block and a memory module. The specialized processing block may be designed with a datapath and operators arranged to support the configuring of a processor element.

Abstract translation: 可编程集成电路器件包括多个可编程逻辑资源簇。 可编程设备互连资源允许可编程逻辑资源集群之间的用户定义的互连。 多个专用处理块具有专用算术运算器和可编程内部互连资源，并具有可编程地连接到可编程器件互连资源的输入和输出。 多个专用存储器模块具有可编程地连接到可编程器件互连资源的输入和输出。 专用处理块中的至少一个相应单独的一个可编程地可连接的直接互连和专用存储器模块中的至少一个相应的独立的一个允许从专门的处理块和存储器模块形成处理器元件。 专门的处理块可以被设计成具有数据路径和被配置为支持处理器元件的配置的操作者。

公开(公告)号：US09245085B2

公开(公告)日：2016-01-26

申请号：US14484655

申请日：2014-09-12

Applicant: Altera Corporation

Inventor： Ryan Fung ,  David Lewis ,  Valavan Manohararajah

IPC: G06F17/50 ,  H03K19/177

CPC classification number: G06F17/5054 ,  G06F17/50 ,  G06F17/5045 ,  G06F17/5059 ,  G06F17/5077 ,  G06F2217/84 ,  H03K19/17728 ,  H03K19/17736

Abstract: A method of configuring an integrated circuit device with a user logic design includes analyzing the user logic design to identify timing requirements of paths within the user logic design, determining latency requirements along those paths, routing the user logic design based on availability of storage elements for incorporation into those paths to satisfy the latency requirements, and retiming the user logic design following that routing by incorporating at least some of the storage elements.

Abstract translation: 配置具有用户逻辑设计的集成电路设备的方法包括分析用户逻辑设计以识别用户逻辑设计内的路径的定时要求，确定沿着这些路径的等待时间要求，基于存储元件的可用性路由用户逻辑设计， 并入到这些路径中以满足等待时间要求，并且通过并入至少一些存储元件来重新定时跟踪该路由之后的用户逻辑设计。

公开(公告)号：US20150134870A1

公开(公告)日：2015-05-14

申请号：US14075802

申请日：2013-11-08

Applicant: Altera Corporation

Inventor： David Galloway ,  David Lewis ,  Ryan Fung ,  Valavan Manohararajah ,  Jeffrey Christopher Chromczak

IPC: G06F1/10

CPC classification number: G06F1/10 ,  G06F1/08 ,  G06F13/4068

Abstract: An integrated circuit may have pipelined programmable interconnects that are configured to select between a routing signal stored in a register and the identical routing signal bypassing the register. The pipelined programmable interconnect may send the selected routing signal over a wire to the next pipelined programmable interconnect circuitry. The integrated circuit may also have clock routing circuitry to select respective clock signals for the registers in the different pipelined programmable interconnects. The clock routing circuitry may include first interconnects that convey region clocks, second interconnects that conveys routing clocks, a first selector circuit to select routing clocks among the region clocks, and a second selector circuit to select routing clocks for the respective registers.

Abstract translation: 集成电路可以具有流水线可编程互连，其被配置为在存储在寄存器中的路由信号与绕过寄存器的相同路由信号之间进行选择。 流水线可编程互连可以通过线将所选择的路由信号发送到下一个流水线可编程互连电路。 集成电路还可以具有时钟路由选择电路，以选择用于不同流水线可编程互连中的寄存器的相应时钟信号。 时钟路由电路可以包括传送区域时钟的第一互连，传送路由时钟的第二互连，第一选择器电路，以选择区域时钟之间的路由时钟;以及第二选择器电路，以选择各个寄存器的路由时钟。