公开(公告)号：US12108604B2

公开(公告)日：2024-10-01

申请号：US17479789

申请日：2021-09-20

Applicant: Applied Materials, Inc.

Inventor： Jaesoo Ahn ,  Thomas Kwon ,  Mahendra Pakala

IPC: H10B51/20 ,  H01L21/02 ,  H01L21/28 ,  H01L21/311 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78

CPC classification number: H10B51/20 ,  H01L21/02164 ,  H01L21/02236 ,  H01L29/40111 ,  H01L29/516 ,  H01L29/517 ,  H01L29/66666 ,  H01L29/6684 ,  H01L29/7827 ,  H01L29/78391 ,  H01L21/02252 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/31116

Abstract: Embodiments of the present disclosure provide an apparatus and methods for forming stair-like structures with accurate profiles and dimension control for manufacturing three dimensional (3D) stacked memory cell semiconductor devices. In one embodiment, a memory cell device includes a film stack comprising alternating pairs of dielectric layers and conductive structures horizontally formed on a substrate, an opening formed in the film stack, wherein the opening is filled with a channel layer and a center filling layer, and a protective liner layer disposed between the conductive structure and the channel layer.

公开(公告)号：US12075628B2

公开(公告)日：2024-08-27

申请号：US17423435

申请日：2020-01-16

Applicant: Applied Materials, Inc.

Inventor： Lin Xue ,  Chando Park ,  Jaesoo Ahn ,  Hsin-wei Tseng ,  Mahendra Pakala

IPC: H10B61/00 ,  G11C11/16 ,  H10N50/80 ,  H10N50/85 ,  H10N50/01

CPC classification number: H10B61/00 ,  G11C11/161 ,  H10N50/80 ,  H10N50/85 ,  H10N50/01

Abstract: Implementations of the present disclosure generally relate to a memory device. More specifically, implementations described herein generally relate to a SOT-MRAM. The SOT-MRAM includes a memory cell having a magnetic storage layer disposed side by side and in contact with a SOT layer. The side by side magnetic storage layer and the SOT layer can achieve the switching of the magnetic storage layer by reversing the direction of the electrical current flowing through the SOT layer without any additional conditions.

公开(公告)号：US20240237337A9

公开(公告)日：2024-07-11

申请号：US18486576

申请日：2023-10-13

Applicant: Applied Materials, Inc.

Inventor： Jaesoo Ahn ,  Jose Alexandro Romero ,  Kunal Bhatnagar ,  Mahendra Pakala

IPC: H10B43/20 ,  H01L21/02

CPC classification number: H10B43/20 ,  H01L21/0228 ,  H10B43/35

Abstract: A method includes obtaining a base structure of a three-dimensional (3D) memory device, forming, on the base structure, a blocking layer including a high-k dielectric material, and forming, on the blocking layer, a wordline for the 3D memory device including molybdenum using an atomic layer deposition (ALD) process.

公开(公告)号：US11069853B2

公开(公告)日：2021-07-20

申请号：US16195313

申请日：2018-11-19

Applicant: Applied Materials, Inc.

Inventor： Hsin-Wei Tseng ,  Chando Park ,  Jaesoo Ahn ,  Lin Xue ,  Mahendra Pakala

IPC: H01L27/22 ,  H01L43/12 ,  H01L43/02 ,  H01L43/10

Abstract: Embodiments of the disclosure provide methods and apparatus for fabricating magnetic tunnel junction (MTJ) structures on a substrate in for hybrid (or called integrated) spin-orbit-torque magnetic spin-transfer-torque magnetic random access memory (SOT-STT MRAM) applications. In one embodiment, the method includes one or more magnetic tunnel junction structures disposed on a substrate, the magnetic tunnel junction structure comprising a first ferromagnetic layer and a second ferromagnetic layer sandwiching a tunneling barrier layer, a spin orbit torque (SOT) layer disposed on the magnetic tunnel junction structure, and a back end structure disposed on the spin orbit torque (SOT) layer.

公开(公告)号：US20210111338A1

公开(公告)日：2021-04-15

申请号：US16601250

申请日：2019-10-14

Applicant: Applied Materials, Inc.

Inventor： Lin XUE ,  Jaesoo Ahn ,  Sahil Patel ,  Chando Park ,  Mahendra Pakala

IPC: H01L43/12 ,  G11B5/39 ,  G11C11/16 ,  H01L43/08

Abstract: A film stack for a magnetic tunnel comprises a substrate, a magnetic reference layer disposed over the substrate, and a tunnel barrier layer disposed over the magnetic reference layer. The film stack further comprises a magnetic storage layer disposed over the tunnel barrier layer, and a capping layer disposed over the magnetic storage layer. Further, the film stack comprises at least one protection layer disposed between the magnetic reference layer and the tunnel barrier layer and disposed between the magnetic storage layer and the capping layer. Additionally, a material forming the at least one protection layer differs from at least one of a material forming the magnetic reference layer and a material forming the magnetic storage layer.

公开(公告)号：US10714388B2

公开(公告)日：2020-07-14

申请号：US16222630

申请日：2018-12-17

Applicant: APPLIED MATERIALS, INC.

Inventor： Jin Hee Park ,  Tae Hong Ha ,  Sang-Hyeob Lee ,  Thomas Jongwan Kwon ,  Jaesoo Ahn ,  Xianmin Tang ,  Er-Xuan Ping ,  Sree Kesapragada

IPC: H01L21/768 ,  H01L21/285 ,  C23C16/48 ,  C23C16/455 ,  C23C16/04 ,  C23C16/16 ,  C23C16/18 ,  C23C16/56 ,  H01L21/67 ,  H01L23/532 ,  H01L27/11556 ,  H01L27/11582

Abstract: Methods and apparatus for depositing a cobalt layer in a feature, such as, a word line formed in a substrate, are provided herein. In some embodiments, method of processing a substrate includes: exposing a substrate at a first temperature to a cobalt containing precursor to deposit a cobalt layer within a word line feature formed in the substrate, wherein the word line feature is part of a 3D NAND device; and annealing the substrate to remove contaminants from the cobalt layer and to reflow the cobalt layer into the word line feature, wherein the substrate is at a second temperature greater than the first temperature during the annealing.

公开(公告)号：US10410864B2

公开(公告)日：2019-09-10

申请号：US15988830

申请日：2018-05-24

Applicant: Applied Materials, Inc.

Inventor： Thomas Jongwan Kwon ,  Rui Cheng ,  Abhijit Basu Mallick ,  Er-Xuan Ping ,  Jaesoo Ahn

IPC: H01L21/033 ,  H01L21/3213 ,  H01L21/02 ,  H01L21/308 ,  H01L21/311 ,  H01L27/11582 ,  H01L49/02

Abstract: Implementations of the present disclosure relate to improved hardmask materials and methods for patterning and etching of substrates. A plurality of hardmasks may be utilized in combination with patterning and etching processes to enable advanced device architectures. In one implementation, a first hardmask and a second hardmask disposed on a substrate having various material layers disposed thereon. The second hardmask may be utilized to pattern the first hardmask during a first etching process. A third hardmask may be deposited over the first and second hardmasks and a second etching process may be utilized to form channels in the material layers.

公开(公告)号：US10255935B2

公开(公告)日：2019-04-09

申请号：US15862301

申请日：2018-01-04

Applicant: Applied Materials, Inc.

Inventor： Lin Xue ,  Chi Hong Ching ,  Jaesoo Ahn ,  Mahendra Pakala ,  Rongjun Wang

IPC: H01L27/20 ,  G11B5/39 ,  G11B5/31 ,  G11C11/15 ,  H01L21/768

Abstract: Embodiments herein provide film stacks utilized to form a magnetic tunnel junction (MTJ) structure on a substrate, comprising: a buffer layer; a seed layer disposed over the buffer layer; a first pinning layer disposed over the seed layer; a synthetic ferrimagnet (SyF) coupling layer disposed over the first pinning layer; a second pinning layer disposed over the SyF coupling layer; a structure blocking layer disposed over the second pinning layer; a magnetic reference layer disposed over the structure blocking layer; a tunnel barrier layer disposed over the magnetic reference layer; a magnetic storage layer disposed over the tunnel barrier layer; a capping layer disposed over the magnetic storage layer, wherein the capping layer comprises one or more layers; and a hard mask disposed over the capping layer, wherein at least one of the capping layer, the buffer layer, and the SyF coupling layer is not fabricated from Ru.