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    Deep trench integration processes and devices
    23.
    发明授权
    Deep trench integration processes and devices 有权

    公开(公告)号：US11410873B2

    公开(公告)日：2022-08-09

    申请号：US16953567

    申请日：2020-11-20

    Applicant: Applied Materials, Inc.

    Inventor： Lan Yu ,  Tyler Sherwood ,  Michael Chudzik ,  Siddarth Krishnan

    IPC: H01L29/00 ,  H01L29/94 ,  H01L31/062 ,  H01L21/768 ,  H01L29/06 ,  H01L21/762

    Abstract: Exemplary methods of forming a semiconductor device may include etching a trench from a first surface of a semiconductor substrate to a first depth within the semiconductor substrate. The trench may be characterized by a first width through the first depth. The methods may include forming a liner along sidewalls of the trench. The methods may include etching the trench to a second depth at least ten times greater than the first depth. The trench may be characterized by a second width through the second depth. The methods may include filling the trench with a dielectric material. A seam formed in the dielectric material may be maintained below the first depth.

    Non-uniform state spacing in multi-state memory element for low-power operation
    24.
    发明授权
    Non-uniform state spacing in multi-state memory element for low-power operation 有权

    公开(公告)号：US11127458B1

    公开(公告)日：2021-09-21

    申请号：US16861204

    申请日：2020-04-28

    Applicant: Applied Materials, Inc.

    Inventor： Deepak Kamalanathan ,  Siddarth Krishnan ,  Fuxi Cai ,  Christophe J Chevallier

    IPC: G11C11/56 ,  G11C13/00

    Abstract: A method of setting multi-state memory elements into at least one low-power state may include receiving a command to cause a memory element to transition into one of three or more states; applying a first signal to the memory element to transition the memory element into the one of the three or more states, where the three or more states are evenly spaced in a portion of an operating range of the memory element; receiving a command to cause a memory element to transition into a low-power state; applying a second signal to the memory element to transition the memory element into the low-power state, where the low-power state is outside of the portion of the operating range of the memory element by an amount greater than a space between each of the three or more states.

    METHODS OF FORMING ABRUPT INTERFACES BETWEEN SILICON-AND-CARBON-CONTAINING MATERIALS AND SILICON-AND-OXYGEN-CONTAINING MATERIALS
    26.
    发明申请
    METHODS OF FORMING ABRUPT INTERFACES BETWEEN SILICON-AND-CARBON-CONTAINING MATERIALS AND SILICON-AND-OXYGEN-CONTAINING MATERIALS 有权

    公开(公告)号：US20250037987A1

    公开(公告)日：2025-01-30

    申请号：US18226579

    申请日：2023-07-26

    Applicant: Applied Materials, Inc.

    Inventor： Stephen Weeks ,  Hansel Lo ,  John Tolle ,  Christopher S. Olsen ,  Siddarth Krishnan

    IPC: H01L21/02

    Abstract: Exemplary semiconductor processing methods may include performing a pre-treatment on a substrate housed within a processing region of a semiconductor processing chamber. The substrate may include a layer of silicon-and-carbon-containing material. The pre-treatment may remove native oxide or residue from a surface of the layer of silicon-and-carbon-containing material. The methods may include providing a silicon-containing precursor to the processing region of the semiconductor processing chamber. The methods may include contacting the substrate with the silicon-containing precursor. The contacting may deposit a layer of silicon-containing material on the layer of silicon-and-carbon-containing material. The methods may include providing an oxygen-containing precursor to the processing region of the semiconductor processing chamber. The methods may include contacting the substrate with the oxygen-containing precursor. The contacting may oxidize the layer of silicon-containing material to form a layer of silicon-and-oxygen-containing material.

    POWER DEVICE STRUCTURES AND METHODS OF MAKING
    27.
    发明公开
    POWER DEVICE STRUCTURES AND METHODS OF MAKING 审中-公开

    公开(公告)号：US20230223256A1

    公开(公告)日：2023-07-13

    申请号：US17572963

    申请日：2022-01-11

    Applicant: Applied Materials, Inc.

    Inventor： Amirhasan Nourbakhsh ,  Raman Gaire ,  Tyler Sherwood ,  Lan Yu ,  Roger Quon ,  Siddarth Krishnan

    IPC: H01L21/02

    CPC classification number: H01L21/02576 ,  H01L21/02579 ,  H01L21/02532

    Abstract: Exemplary semiconductor processing methods may include forming a p-type silicon-containing material on a substrate including a first n-type silicon-containing material defining one or more features. The p-type silicon-containing material may extend along at least a portion of the one or more features defined in the first n-type silicon-containing material. The methods may include removing a portion of the p-type silicon-containing material. The portion of the p-type silicon-containing material may be removed from a bottom of the one or more features. The methods may include providing a silicon-containing material. The methods may include depositing a second n-type silicon-containing material on the substrate. The second n-type silicon-containing material may fill the one or more features formed in the first n-type silicon-containing material and may separate regions of remaining p-type silicon-containing material.

    GRADED DOPING IN POWER DEVICES
    28.
    发明申请
    GRADED DOPING IN POWER DEVICES 有权

    公开(公告)号：US20220254886A1

    公开(公告)日：2022-08-11

    申请号：US17169916

    申请日：2021-02-08

    Applicant: Applied Materials, Inc.

    Inventor： Ashish Pal ,  El Mehdi Bazizi ,  Siddarth Krishnan ,  Xing Chen ,  Lan Yu ,  Tyler Sherwood

    IPC: H01L29/36 ,  H01L29/872 ,  H01L21/02 ,  H01L21/265 ,  H01L21/285 ,  H01L21/3065 ,  H01L29/66

    Abstract: Exemplary methods of forming a semiconductor structure may include forming a doped silicon layer on a semiconductor substrate. A level of doping may be increased at an increasing distance from the semiconductor substrate. The methods may include etching the doped silicon layer to define a trench extending to the semiconductor substrate. The doped silicon layer may define a sloping sidewall of the trench. The trench may be characterized by a depth of greater than or about 30 μm. The methods may include lining the trench with a first oxide material. The methods may include depositing a second oxide material within the trench. The methods may include forming a contact to produce a power device.

    DEEP TRENCH INTEGRATION PROCESSES AND DEVICES
    29.
    发明申请
    DEEP TRENCH INTEGRATION PROCESSES AND DEVICES 有权

    公开(公告)号：US20220165610A1

    公开(公告)日：2022-05-26

    申请号：US16953567

    申请日：2020-11-20

    Applicant: Applied Materials, Inc.

    Inventor： Lan Yu ,  Tyler Sherwood ,  Michael Chudzik ,  Siddarth Krishnan

    IPC: H01L21/768 ,  H01L21/762 ,  H01L29/06

    Abstract: Exemplary methods of forming a semiconductor device may include etching a trench from a first surface of a semiconductor substrate to a first depth within the semiconductor substrate. The trench may be characterized by a first width through the first depth. The methods may include forming a liner along sidewalls of the trench. The methods may include etching the trench to a second depth at least ten times greater than the first depth. The trench may be characterized by a second width through the second depth. The methods may include filling the trench with a dielectric material. A seam formed in the dielectric material may be maintained below the first depth.

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