公开(公告)号：US20150262829A1

公开(公告)日：2015-09-17

申请号：US14215701

申请日：2014-03-17

Applicant: Applied Materials, Inc.

Inventor： Seung Park ,  Xikun Wang ,  Jie Liu ,  Anchuan Wang ,  Sang-jin Kim

IPC: H01L21/3065

CPC classification number: H01L21/3065 ,  H01J37/32357 ,  H01J2237/334 ,  H01L21/32136

Abstract: Methods of evenly etching tungsten liners from high aspect ratio trenches are described. The methods include a remote plasma etch using plasma effluents formed from a fluorine-containing precursor and a high flow of helium. Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents react with tungsten coating a patterned substrate having high aspect ratio trenches. The plasmas effluents react with exposed surfaces and evenly remove tungsten from outside the trenches and on the sidewalls of the trenches. The plasma effluents pass through an ion suppression element positioned between the remote plasma and the substrate processing region. Optionally, the methods may include concurrent ion bombardment of the patterned substrate to help remove potentially thicker horizontal tungsten regions, e.g., at the bottom of the trenches or between trenches.

Abstract translation: 描述了从高纵横比沟槽均匀地蚀刻钨衬垫的方法。 这些方法包括使用由含氟前体形成的等离子体流出物和大量氦气的远程等离子体蚀刻。 来自远程等离子体的等离子体流出物流入衬底处理区域，其中等离子体流出物与钨涂覆具有高纵横比沟槽的图案化衬底。 等离子体流出物与暴露的表面反应，并从沟槽的外部和沟槽的侧壁均匀地除去钨。 等离子体流出物通过位于远程等离子体和基板处理区域之间的离子抑制元件。 可选地，所述方法可以包括图案化衬底的同时离子轰击，以帮助去除潜在的较厚的水平钨区域，例如在沟槽的底部或沟槽之间。

公开(公告)号：US20150179464A1

公开(公告)日：2015-06-25

申请号：US14617779

申请日：2015-02-09

Applicant: Applied Materials, Inc.

Inventor： Xikun Wang ,  Ching-Mei Hsu ,  Nitin K. Ingle ,  Zihui Li ,  Anchuan Wang

IPC: H01L21/3065 ,  H01L21/02

CPC classification number: H01L21/3065 ,  H01J37/32357 ,  H01L21/02049 ,  H01L21/32136

Abstract: Methods of selectively etching tungsten relative to silicon-containing films (e.g. silicon oxide, silicon carbon nitride and (poly)silicon) as well as tungsten oxide are described. The methods include a remote plasma etch formed from a fluorine-containing precursor and/or hydrogen (H2). Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents react with the tungsten. The plasma effluents react with exposed surfaces and selectively remove tungsten while very slowly removing other exposed materials. Sequential and simultaneous methods are included to remove thin tungsten oxide which may, for example, result from exposure to the atmosphere.

Abstract translation: 描述了相对于含硅膜（例如氧化硅，氮化碳和（多）硅）选择性地蚀刻钨的方法以及氧化钨。 这些方法包括由含氟前体和/或氢（H 2）形成的远程等离子体蚀刻。 来自远程等离子体的等离子体流出物流入基板处理区域，其中等离子体流出物与钨反应。 等离子体流出物与暴露的表面反应并选择性地去除钨，同时非常缓慢地除去其它暴露的材料。 包括顺序和同时的方法以除去例如由于暴露于大气中而产生的薄氧化钨。

公开(公告)号：US20150129546A1

公开(公告)日：2015-05-14

申请号：US14513517

申请日：2014-10-14

Applicant: Applied Materials, Inc.

Inventor： Nitin K. Ingle ,  Jessica Sevanne Kachian ,  Lin Xu ,  Soonam Park ,  Xikun Wang ,  Jeffrey W. Anthis

IPC: C23F1/12 ,  C23F1/02

CPC classification number: H01L21/3065 ,  C23F1/02 ,  C23F1/12 ,  C23F4/00 ,  H01J37/3244 ,  H01J2237/334 ,  H01J2237/3341 ,  H01L21/02071 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/32135 ,  H01L21/32136 ,  H01L21/76814

Abstract: Methods of selectively etching metal-containing materials from the surface of a substrate are described. The etch selectively removes metal-containing materials relative to silicon-containing films such as silicon, polysilicon, silicon oxide, silicon germanium, silicon carbide, silicon carbon nitride and/or silicon nitride. The methods include exposing metal-containing materials to halogen containing species in a substrate processing region. No plasma excites the halogen-containing precursor either remotely or locally in embodiments.

Abstract translation: 描述了从衬底表面选择性地蚀刻含金属材料的方法。 蚀刻相对于含硅膜如硅，多晶硅，氧化硅，硅锗，碳化硅，氮化硅和/或氮化硅选择性去除含金属的材料。 这些方法包括将含金属的材料暴露于基底处理区域中含有卤素的物质。 在实施例中，没有等离子体远程地或局部地激发含卤素的前体。

公开(公告)号：US11462411B2

公开(公告)日：2022-10-04

申请号：US17242375

申请日：2021-04-28

Applicant: Applied Materials, Inc.

Inventor： Gaurav Thareja ,  Keyvan Kashefizadeh ,  Xikun Wang ,  Anchuan Wang ,  Sanjay Natarajan ,  Sean M. Seutter ,  Dong Wu

IPC: H01L21/283 ,  H01L29/49 ,  H01L21/28 ,  H01L29/45

Abstract: A semiconductor device fabrication process includes forming gates on a substrate having a plurality of openings, each gate having a conducting layer a first metal and a gate dielectric layer of a first dielectric material, partially filling the openings with a second dielectric material, forming a first structure on the substrate in a processing system without breaking vacuum, depositing a third dielectric material over the first structure, and forming a planarized surface of the gates and a surface of the third dielectric material that is disposed over the first structure. The forming of the first structure includes forming trenches by removing second portions of the second dielectric material within each opening, forming recessed active regions in the trenches by partially filling the trenches with a second metal, forming a liner over each recessed active region, and forming a metal cap layer over each liner.

公开(公告)号：US11004687B2

公开(公告)日：2021-05-11

申请号：US16442797

申请日：2019-06-17

Applicant: Applied Materials, Inc.

Inventor： Gaurav Thareja ,  Keyvan Kashefizadeh ,  Xikun Wang ,  Anchuan Wang ,  Sanjay Natarajan ,  Sean M. Seutter ,  Dong Wu

IPC: H01L21/28 ,  H01L29/49 ,  H01L29/45 ,  H01L21/283

Abstract: A semiconductor device fabrication process includes forming gates on a substrate having a plurality of openings, each gate having a conducting layer a first metal and a gate dielectric layer of a first dielectric material, partially filling the openings with a second dielectric material, forming a first structure on the substrate in a processing system without breaking vacuum, depositing a third dielectric material over the first structure, and forming a planarized surface of the gates and a surface of the third dielectric material that is disposed over the first structure. The forming of the first structure includes forming trenches by removing second portions of the second dielectric material within each opening, forming recessed active regions in the trenches by partially filling the trenches with a second metal, forming a liner over each recessed active region, and forming a metal cap layer over each liner.

公开(公告)号：US20180138085A1

公开(公告)日：2018-05-17

申请号：US15349460

申请日：2016-11-11

Applicant: Applied Materials, Inc.

Inventor： Xikun Wang ,  Jianxin Lei ,  Nitin Ingle ,  Roey Shaviv

IPC: H01L21/768 ,  H01L21/3213 ,  H01L23/532 ,  H01L21/321 ,  H01L21/67

CPC classification number: H01L21/76877 ,  H01L21/321 ,  H01L21/32135 ,  H01L21/32136 ,  H01L21/67069 ,  H01L21/76883 ,  H01L23/53209

Abstract: Exemplary methods for removing cobalt material may include flowing a chlorine-containing precursor into a processing region of a semiconductor processing chamber. The methods may include forming a plasma of the chlorine-containing precursor to produce plasma effluents. The methods may also include contacting an exposed region of cobalt with the plasma effluents. The exposed region of cobalt may include an overhang of cobalt on a trench defined on a substrate. The plasma effluents may produce cobalt chloride at the overhang of cobalt. The methods may include flowing a nitrogen-containing precursor into the processing region of the semiconductor processing chamber. The methods may further include contacting the cobalt chloride with the nitrogen-containing precursor. The methods may also include recessing the overhang of cobalt.

公开(公告)号：US09947549B1

公开(公告)日：2018-04-17

申请号：US15332849

申请日：2016-10-24

Applicant: Applied Materials, Inc.

Inventor： Xikun Wang ,  Zhenjiang Cui ,  Soonam Park ,  Nitin K. Ingle

IPC: H01L21/302 ,  H01L21/461 ,  B44C1/22 ,  C03C15/00 ,  C03C25/68 ,  C23F1/00 ,  C23F3/00 ,  H01L21/3213 ,  H01L21/311 ,  C23F1/12 ,  H01J37/32 ,  H01L21/768 ,  H01L21/02 ,  H01L21/3065

CPC classification number: H01L21/32136 ,  C23F1/12 ,  H01J37/32091 ,  H01J37/3244 ,  H01J2237/334 ,  H01L21/02071 ,  H01L21/3065 ,  H01L21/31122 ,  H01L21/32135 ,  H01L21/32138 ,  H01L21/7684

Abstract: Methods are described herein for etching cobalt films which are difficult to volatize. The methods include exposing a cobalt film to a bromine or chlorine-containing precursor with a concurrent local plasma which applies a bias to the impinging etchants. Cobalt halide is formed on the surface at the same time an amorphized cobalt layer is formed near the surface. A carbon-and-nitrogen-containing precursor is later delivered to the substrate processing region to form volatile cobalt complexes which desorb from the surface of the cobalt film. Cobalt may be selectively removed. The concurrent production of cobalt halide and amorphized regions was found to markedly increase the overall etch rate and markedly improve surface smoothness upon exposure to the carbon-and-nitrogen-containing precursor. All the recited steps may now be performed in the same substrate processing chamber.

公开(公告)号：US20180102259A1

公开(公告)日：2018-04-12

申请号：US15332849

申请日：2016-10-24

Applicant: Applied Materials, Inc.

Inventor： Xikun Wang ,  Zhenjiang Cui ,  Soonam Park ,  Nitin K. Ingle

IPC: H01L21/3213 ,  H01L21/311 ,  C23F1/12 ,  H01J37/32

CPC classification number: H01L21/32136 ,  C23F1/12 ,  H01J37/32091 ,  H01J37/3244 ,  H01J2237/334 ,  H01L21/02071 ,  H01L21/3065 ,  H01L21/31122 ,  H01L21/32135 ,  H01L21/32138 ,  H01L21/7684

Abstract: Methods are described herein for etching cobalt films which are difficult to volatize. The methods include exposing a cobalt film to a bromine or chlorine-containing precursor with a concurrent local plasma which applies a bias to the impinging etchants. Cobalt halide is formed on the surface at the same time an amorphized cobalt layer is formed near the surface. A carbon-and-nitrogen-containing precursor is later delivered to the substrate processing region to form volatile cobalt complexes which desorb from the surface of the cobalt film. Cobalt may be selectively removed. The concurrent production of cobalt halide and amorphized regions was found to markedly increase the overall etch rate and markedly improve surface smoothness upon exposure to the carbon-and-nitrogen-containing precursor. All the recited steps may now be performed in the same substrate processing chamber.

公开(公告)号：US20170096740A1

公开(公告)日：2017-04-06

申请号：US15383556

申请日：2016-12-19

Applicant: Applied Materials, Inc.

Inventor： Benjamin Schmiege ,  Nitin K. Ingle ,  Srinivas D. Nemani ,  Jeffrey W. Anthis ,  Xikun Wang ,  Jie Liu ,  David Benjaminson

IPC: C23F1/12 ,  H01J37/32

CPC classification number: C23F1/12 ,  C23F4/00 ,  C30B33/12 ,  H01J37/32009 ,  H01J2237/334

Abstract: Provided are methods for etching films comprising transition metals which help to minimize higher etch rates at the grain boundaries of polycrystalline materials. Certain methods pertain to amorphization of the polycrystalline material, other pertain to plasma treatments, and yet other pertain to the use of small doses of halide transfer agents in the etch process.

公开(公告)号：US09449846B2

公开(公告)日：2016-09-20

申请号：US14607883

申请日：2015-01-28

Applicant: Applied Materials, Inc.

Inventor： Jie Liu ,  Vinod R. Purayath ,  Xikun Wang ,  Anchuan Wang ,  Nitin K. Ingle

IPC: H01L21/302 ,  H01L21/3213 ,  H01L21/8234 ,  H01L27/115

CPC classification number: H01L21/32136 ,  H01J37/32357 ,  H01J37/32422 ,  H01J37/3244 ,  H01J37/32954 ,  H01L21/32135 ,  H01L21/823437 ,  H01L27/11582

Abstract: Methods of selectively etching tungsten from the surface of a patterned substrate are described. The methods electrically separate vertically arranged tungsten slabs from one another as needed. The vertically arranged tungsten slabs may form the walls of a trench during manufacture of a vertical flash memory cell. The tungsten etch may selectively remove tungsten relative to films such as silicon, polysilicon, silicon oxide, aluminum oxide, titanium nitride and silicon nitride. The methods include exposing electrically-shorted tungsten slabs to remotely-excited fluorine formed in a remote plasma region. Process parameters are provided which result in uniform tungsten recess within the trench. A low electron temperature is maintained in the substrate processing region to achieve high etch selectivity and uniform removal throughout the trench.

Abstract translation: 描述了从图案化衬底的表面选择性地蚀刻钨的方法。 所述方法根据需要将垂直排列的钨板彼此电分离。 在垂直闪存单元的制造期间，垂直布置的钨板可以形成沟槽的壁。 钨蚀刻可以相对于诸如硅，多晶硅，氧化硅，氧化铝，氮化钛和氮化硅的膜选择性地去除钨。 这些方法包括将电短路钨板暴露于在远程等离子体区域中形成的远程激发的氟。 提供了在沟槽内产生均匀的钨凹槽的工艺参数。 在基板处理区域中保持低电子温度，以实现高蚀刻选择性并且在整个沟槽中均匀地去除。