公开(公告)号：US11508584B2

公开(公告)日：2022-11-22

申请号：US16900181

申请日：2020-06-12

Applicant: Applied Materials, Inc.

Inventor： Sean M. Seutter ,  Mun Kyu Park ,  Hien M Le ,  Chih-Chiang Chuang

IPC: H01L21/30 ,  C23C16/28 ,  C23C16/455 ,  H01L21/768 ,  H01L21/265 ,  H01L21/223

Abstract: Films are modified to include deuterium in an inductive high density plasma chamber. Chamber hardware designs enable tunability of the deuterium concentration uniformity in the film across a substrate. Manufacturing of solid state electronic devices include integrated process flows to modify a film that is substantially free of hydrogen and deuterium to include deuterium.

公开(公告)号：US11370669B2

公开(公告)日：2022-06-28

申请号：US16247123

申请日：2019-01-14

Applicant: Applied Materials, Inc.

Inventor： Tatsuya E. Sato ,  Li-Qun Xia ,  Sean M. Seutter

IPC: C23C16/455 ,  C01F17/218 ,  H01L21/02 ,  C23C16/40 ,  C09D1/00

Abstract: Amorphous silicon doped yttrium oxide films and methods of making same are described. Deposition of the amorphous silicon doped yttrium oxide film by thermal chemical vapor deposition or atomic layer deposition process are described.

公开(公告)号：US20230037450A1

公开(公告)日：2023-02-09

申请号：US17968056

申请日：2022-10-18

Applicant: Applied Materials, Inc.

Inventor： Sean M. Seutter ,  Mun Kyu Park ,  Hien M Le ,  Chih-Chiang Chuang

IPC: H01L21/30 ,  C23C16/28 ,  C23C16/455 ,  H01L21/768 ,  H01L21/265 ,  H01L21/223

Abstract: Films are modified to include deuterium in an inductive high density plasma chamber. Chamber hardware designs enable tunability of the deuterium concentration uniformity in the film across a substrate. Manufacturing of solid state electronic devices include integrated process flows to modify a film that is substantially free of hydrogen and deuterium to include deuterium.

公开(公告)号：US20220005723A1

公开(公告)日：2022-01-06

申请号：US17368134

申请日：2021-07-06

Applicant: Applied Materials, Inc.

Inventor： Hanish Kumar Panavalappil Kumarankutty ,  Sean M. Seutter ,  Sudhir R. Gondhalekar ,  Wendell Glenn Boyd, JR. ,  Badri Ramamurthi ,  Shekhar Athani ,  Anil Kumar Kalal ,  Jay Dee Pinson, II

IPC: H01L21/683 ,  H01J37/32

Abstract: Embodiments of the disclosure provide electrostatic chucks for securing substrates during processing. Some embodiments of this disclosure provide methods and apparatus for increased temperature control across the radial profile of the substrate. Some embodiments of the disclosure provide methods and apparatus for providing control of hydrogen concentration in processed films during a high-density plasma (HDP) process.

公开(公告)号：US20190221426A1

公开(公告)日：2019-07-18

申请号：US16247123

申请日：2019-01-14

Applicant: Applied Materials, Inc.

Inventor： Tatsuya E. Sato ,  Li-Qun Xia ,  Sean M. Seutter

IPC: H01L21/02 ,  C01F17/00 ,  C09D1/00 ,  C23C16/40 ,  C23C16/455

CPC classification number: H01L21/02192 ,  C01F17/0043 ,  C01P2002/54 ,  C09D1/00 ,  C23C16/405 ,  C23C16/45553 ,  H01L21/0228

Abstract: Amorphous silicon doped yttrium oxide films and methods of making same are described. Deposition of the amorphous silicon doped yttrium oxide film by thermal chemical vapor deposition or atomic layer deposition process are described.

公开(公告)号：US11462411B2

公开(公告)日：2022-10-04

申请号：US17242375

申请日：2021-04-28

Applicant: Applied Materials, Inc.

Inventor： Gaurav Thareja ,  Keyvan Kashefizadeh ,  Xikun Wang ,  Anchuan Wang ,  Sanjay Natarajan ,  Sean M. Seutter ,  Dong Wu

IPC: H01L21/283 ,  H01L29/49 ,  H01L21/28 ,  H01L29/45

Abstract: A semiconductor device fabrication process includes forming gates on a substrate having a plurality of openings, each gate having a conducting layer a first metal and a gate dielectric layer of a first dielectric material, partially filling the openings with a second dielectric material, forming a first structure on the substrate in a processing system without breaking vacuum, depositing a third dielectric material over the first structure, and forming a planarized surface of the gates and a surface of the third dielectric material that is disposed over the first structure. The forming of the first structure includes forming trenches by removing second portions of the second dielectric material within each opening, forming recessed active regions in the trenches by partially filling the trenches with a second metal, forming a liner over each recessed active region, and forming a metal cap layer over each liner.

公开(公告)号：US11004687B2

公开(公告)日：2021-05-11

申请号：US16442797

申请日：2019-06-17

Applicant: Applied Materials, Inc.

Inventor： Gaurav Thareja ,  Keyvan Kashefizadeh ,  Xikun Wang ,  Anchuan Wang ,  Sanjay Natarajan ,  Sean M. Seutter ,  Dong Wu

IPC: H01L21/28 ,  H01L29/49 ,  H01L29/45 ,  H01L21/283

Abstract: A semiconductor device fabrication process includes forming gates on a substrate having a plurality of openings, each gate having a conducting layer a first metal and a gate dielectric layer of a first dielectric material, partially filling the openings with a second dielectric material, forming a first structure on the substrate in a processing system without breaking vacuum, depositing a third dielectric material over the first structure, and forming a planarized surface of the gates and a surface of the third dielectric material that is disposed over the first structure. The forming of the first structure includes forming trenches by removing second portions of the second dielectric material within each opening, forming recessed active regions in the trenches by partially filling the trenches with a second metal, forming a liner over each recessed active region, and forming a metal cap layer over each liner.