公开(公告)号：US20250112052A1

公开(公告)日：2025-04-03

申请号：US18478878

申请日：2023-09-29

Applicant: Applied Materials, Inc.

Inventor： Yi-Hsin CHEN ,  Kevin R. Anglin ,  Yong Yang ,  Solomon Belangedi Basame ,  Yung-Chen Lin ,  Gang Shu

IPC: H01L21/3065

Abstract: Disclosed herein are methods for forming opening ends within semiconductor structures. In some embodiments, a method may include providing an opening formed in a layer of a semiconductor device, wherein the opening comprises a set of sidewalls opposite one another, and first and second end walls connected to the sidewalls, wherein each of the first and second end walls defines a tip end and a set of curved sections extending between the tip end and the set of sidewall. The method may further include performing an ion etch to the opening by delivering an ion beam at a non-zero angle relative to a plane defined by the layer of the semiconductor device, wherein the ion etch comprises a lean-gas chemistry, and wherein the ion etch causes the layer of the semiconductor device to be removed faster along the set of curved sections than along the set of sidewalls.

公开(公告)号：US12230688B2

公开(公告)日：2025-02-18

申请号：US17667036

申请日：2022-02-08

Applicant: Applied Materials, Inc.

Inventor： Yong Yang ,  Srinivas Gandikota ,  Steven C. H. Hung ,  Mandyam Sriram ,  Jacqueline S. Wrench ,  Yixiong Yang

IPC: H01L29/51 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78

Abstract: A metal gate stack on a substrate comprises: an interfacial layer on the substrate; a high-κ metal oxide layer on the interfacial layer, the high-κ metal oxide layer comprising a dipole region adjacent to the interfacial layer, the dipole region comprising niobium (Nb); a high-κ metal oxide capping layer on the high-κ metal oxide layer; a positive metal-oxide-semiconductor (PMOS) work function material above the high-κ metal oxide capping layer; and a gate electrode above the PMOS work function material. The dipole region is formed by driving Nb species of a Nb-based film into the high-κ metal oxide layer to form a dipole region.

公开(公告)号：US20240060175A1

公开(公告)日：2024-02-22

申请号：US17891753

申请日：2022-08-19

Applicant: Applied Materials, Inc.

Inventor： Srinivas Gandikota ,  Yixiong Yang ,  Yong Yang ,  Tuerxun Ailihumaer ,  Yogesh Sharma ,  Kunal Bhatnagar ,  Mohith Verghese

IPC: C23C16/06 ,  H01L21/285 ,  C23C16/455

CPC classification number: C23C16/06 ,  H01L21/28556 ,  C23C16/45553

Abstract: Embodiments of the disclosure provide conformally deposited molybdenum films having reduced resistivity and methods of forming the same. The methods include forming a nucleation layer directly on a dielectric layer on a substrate surface by exposing the substrate surface to a molybdenum-containing precursor and a nucleation reactant, and conformally depositing a molybdenum film on the nucleation layer. Another aspect of the disclosure pertains to a method that is part of a gap fill process, comprising forming a nucleation layer directly on a dielectric region within one or more high aspect ratio gap features, including vertical gap features and/or horizontal gap features, and conformally depositing a molybdenum film on the nucleation layer to fill the feature.

公开(公告)号：US11587936B2

公开(公告)日：2023-02-21

申请号：US17335287

申请日：2021-06-01

Applicant: Applied Materials, Inc.

Inventor： Yixiong Yang ,  Jacqueline S. Wrench ,  Yong Yang ,  Srinivas Gandikota ,  Annamalai Lakshmanan ,  Joung Joo Lee ,  Feihu Wang ,  Seshadri Ganguli

IPC: H01L27/108 ,  H01L21/285 ,  C23C16/455 ,  H01L21/02 ,  H01L21/8234

Abstract: Methods for DRAM device with a buried word line are described. The method includes forming a metal cap layer and a molybdenum conductor layer in a feature on a substrate. The method includes depositing the metal cap layer on the substrate by physical vapor deposition (PVD) and depositing the molybdenum conductor layer by atomic layer deposition (ALD) on the metal cap layer.

公开(公告)号：US11417517B2

公开(公告)日：2022-08-16

申请号：US16951858

申请日：2020-11-18

Applicant: Applied Materials, Inc.

Inventor： Srinivas Gandikota ,  Yixiong Yang ,  Jacqueline Samantha Wrench ,  Yong Yang ,  Steven C. H. Hung

IPC: H01L21/02 ,  H01L21/28 ,  H01L21/67

Abstract: A method of forming a high-K dielectric cap layer on a semiconductor structure formed on a substrate includes depositing the high-K dielectric cap layer on the semiconductor structure, depositing a sacrificial silicon cap layer on the high-K dielectric cap layer, performing a post cap anneal process to harden and densify the as-deposited high-K dielectric cap layer, and removing the sacrificial silicon cap layer.