公开(公告)号：US10296350B2

公开(公告)日：2019-05-21

申请号：US14673889

申请日：2015-03-31

Applicant: CENTIPEDE SEMI LTD.

Inventor： Noam Mizrahi ,  Alberto Mandler ,  Shay Koren ,  Jonathan Friedmann

IPC: G06F9/38 ,  G06F9/30

Abstract: A method which includes, in a processor that processes instructions of program code, processing one or more of the instructions by a first hardware thread. Upon detecting that an instruction defined as a parallelization point has been fetched for the first thread, a second hardware thread is invoked to process at least one of the instructions at least partially in parallel with processing of the instructions by the first hardware thread.

公开(公告)号：US10013255B2

公开(公告)日：2018-07-03

申请号：US15077936

申请日：2016-03-23

Applicant: Centipede Semi Ltd.

Inventor： Jonathan Friedmann ,  Ido Goren ,  Shay Koren ,  Noam Mizrahi ,  Alberto Mandler

IPC: G06F9/38 ,  G06F9/40 ,  G06F9/45 ,  G06F9/30 ,  G06F8/41 ,  G06F9/455

CPC classification number: G06F9/30058 ,  G06F8/443 ,  G06F9/30061 ,  G06F9/30065 ,  G06F9/30072 ,  G06F9/30079 ,  G06F9/3808 ,  G06F9/3842 ,  G06F9/3844 ,  G06F9/3867 ,  G06F9/45516

Abstract: A method includes, in a processor, processing a sequence of pre-compiled instructions by an instruction pipeline of the processor. A first block of instructions is identified in the instructions flowing via the pipeline. The first block includes a conditional branch instruction that conditionally diverges execution of the instructions into at least first and second flow-control traces that differ from one another in multiple instructions and converge at a given instruction that is again common to the first and second flow-control traces. A second block of instructions, which is logically equivalent to the first block but replaces the first and second flow-control traces by a single flow-control trace, is created by the processor at runtime. The pipeline is caused to execute the second block instead of the first block.

公开(公告)号：US20180129500A1

公开(公告)日：2018-05-10

申请号：US15616970

申请日：2017-06-08

Applicant: Centipede Semi Ltd.

Inventor： Shay Koren ,  Noam Mizrahi ,  Jonathan Friedmann

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30058 ,  G06F9/30065 ,  G06F9/30105 ,  G06F9/3016 ,  G06F9/3804 ,  G06F9/3806 ,  G06F9/3808 ,  G06F9/381 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3855 ,  G06F9/3859

Abstract: A method includes retrieving to a pipeline of a processor first instructions of program code from a first region in the program code. Before fully determining a flow-control path, which is to be traversed within the first region until exit from the first region, a beginning of a second region in the code that is to be processed following the first region is predicted, and second instructions begin to be retrieved to the pipeline from the second region. The retrieved first instructions and second instructions are processed by the pipeline.

公开(公告)号：US20180004627A1

公开(公告)日：2018-01-04

申请号：US15196071

申请日：2016-06-29

Applicant: Centipede Semi Ltd.

Inventor： Shay Koren ,  Arie Hacohen Ben Porat ,  Ido Goren ,  Noam Mizrahi ,  Jonathan Friedmann

IPC: G06F11/36 ,  G06F9/38 ,  G06F9/30

CPC classification number: G06F11/3644 ,  G06F9/30058 ,  G06F9/3808 ,  G06F9/3838 ,  G06F9/3861 ,  G06F11/3466

Abstract: A processor includes an instruction pipeline and control circuitry. The instruction pipeline is configured to process instructions of program code. The control circuitry is configured to monitor the processed instructions at run-time, to construct an invocation data structure comprising multiple entries, wherein each entry (i) specifies an initial instruction that is a target of a branch instruction, (ii) specifies a portion of the program code that follows one or more possible flow-control traces beginning from the initial instruction, and (iii) specifies, for each possible flow-control trace specified in the entry, a next entry that is to be processed following processing of that possible flow-control trace, and to configure the instruction pipeline to process segments of the program code, by continually traversing the entries of the invocation data structure.

公开(公告)号：US09715390B2

公开(公告)日：2017-07-25

申请号：US14690424

申请日：2015-04-19

Applicant: Centipede Semi Ltd.

Inventor： Noam Mizrahi ,  Alberto Mandler ,  Shay Koren ,  Jonathan Friedmann

IPC: G06F9/38 ,  G06F12/0831

CPC classification number: G06F9/3861 ,  G06F9/3808 ,  G06F9/382 ,  G06F9/3832 ,  G06F9/3838 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3875 ,  G06F9/455 ,  G06F9/46 ,  G06F12/0833

Abstract: A method includes, in a processor that processes instructions of program code, processing a first segment of the instructions. One or more destination registers are identified in the first segment using an approximate specification of register access by the instructions. Respective values of the destination registers are made available to a second segment of the instructions only upon verifying that the values are valid for readout by the second segment in accordance with the approximate specification. The second segment is processed at least partially in parallel with processing of the first segment, using the values made available from the first segment.

公开(公告)号：US20160291979A1

公开(公告)日：2016-10-06

申请号：US14673889

申请日：2015-03-31

Applicant: CENTIPEDE SEMI LTD.

Inventor： Noam Mizrahi ,  Alberto Mandler ,  Shay Koren ,  Jonathan Friedmann

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3851 ,  G06F9/30065 ,  G06F9/3808 ,  G06F9/3838

Abstract: A method includes, in a processor that processes instructions of program code, processing one or more of the instructions by a first hardware thread. Upon detecting that an instruction defined as a parallelization point has been fetched for the first thread, a second hardware thread is invoked to process at least one of the instructions at least partially in parallel with processing of the instructions by the first hardware thread.

Abstract translation: 一种方法包括在处理程序代码指令的处理器中，通过第一硬件线程处理一个或多个指令。 在检测到已经为第一线程获取定义为并行化点的指令时，调用第二硬件线程以至少部分地与第一硬件线程对指令的处理并行地处理指令中的至少一个。

公开(公告)号：US09135015B1

公开(公告)日：2015-09-15

申请号：US14583119

申请日：2014-12-25

Applicant: Centipede Semi Ltd.

Inventor： Noam Mizrahi ,  Alberto Mandler ,  Shay Koren ,  Jonathan Friedmann

IPC: G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3861 ,  G06F9/3808 ,  G06F9/3838 ,  G06F9/3851 ,  G06F11/1402 ,  G06F11/30 ,  G06F11/302 ,  G06F11/3055 ,  G06F11/3065 ,  G06F11/3466

Abstract: A method includes, in a processor that executes instructions of program code, monitoring the instructions in a segment of a repetitive sequence of the instructions so as to construct a specification of register access by the monitored instructions. In response to detecting a branch mis-prediction in the monitored instructions, the specification is corrected so as to compensate for the branch mis-prediction. Execution of the repetitive sequence is parallelized based on the corrected specification.

Abstract translation: 一种方法包括在执行程序代码的指令的处理器中监视指令的重复序列的段中的指令，以便构建被监视指令的寄存器访问的规范。 响应于检测到所监视的指令中的分支误差预测，修正说明书以补偿分支误预测。 基于修正后的规格，重复序列的执行是并行化的。