公开(公告)号：US5974627A

公开(公告)日：1999-11-02

申请号：US88954

申请日：1998-06-02

Applicant: Chien-Chung Huang

Inventor： Chien-Chung Huang

IPC: H05K5/02 ,  A47B95/02

CPC classification number: H05K5/023 ,  Y10S16/90 ,  Y10T16/4559 ,  Y10T16/469

Abstract: A handle for a SMIF pod having a handle member with two arms, connected by a crosspiece, and two attachment members, connected respectively to the free ends of the arms, that are attached to two existing handles on the side of a SMIF pod, and wherein the arms are arranged at an angle of about 20.degree. outwardly from the plane of the side of the SMIF pod, and at an angle in the range from 15-45.degree., preferably about 40.degree., upwardly from the plane of the attachment means, so that the handle member, which may be of plastic, can be gripped in such a way that a technician's wrists may be kept straight while lifting the pod and reorienting it during handling, and the handle is compatible for use with existing SMIF pods without requiring their modification.

Abstract translation: 用于具有手柄构件的手柄，其具有两个臂，通过横档连接，两个连接构件分别连接到臂的自由端，其连接到SMIF舱的侧面上的两个现有手柄;以及 其中所述臂从所述SMIF荚的侧面的外侧向外约20度的角度布置，并且在所述附接装置的平面上向上倾斜15-45°，优选约40° ，使得手柄构件（其可以是塑料的）可以以这样的方式被夹持，使得技术人员的手腕可以在提起吊架期间保持直立并在搬运期间重新定向，并且手柄与现有的SMIF荚可以相容地使用，而没有 需要修改。

公开(公告)号：US20120181635A1

公开(公告)日：2012-07-19

申请号：US13424398

申请日：2012-03-20

Applicant: Yi-Wei Chen ,  Nien-Ting Ho ,  Kuo-Chih Lai ,  Chien-Chung Huang

Inventor： Yi-Wei Chen ,  Nien-Ting Ho ,  Kuo-Chih Lai ,  Chien-Chung Huang

IPC: H01L29/78

CPC classification number: H01L29/665 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/28518 ,  H01L21/823443 ,  H01L21/823835 ,  H01L29/6659 ,  H01L29/7833

Abstract: In a method of the present invention during a salicide process, before a second thermal process, a dopant is implanted at a place located in a region ranging from a NixSi layer at meddle height down to a front thereof, or before formation of the NixSi layer, located in a region ranging from a silicon layer at a depth ranging from a half of a predetermined thickness of a NiSi layer down to a depth where is a predetermined front of the NiSi layer. The dopant is allowed to be heated with the NixSi layer together during the second thermal process to form a Si/NiSi2/NiSi interface which may reduce SBH and improve series resistance to obtain a semiconductor device having an excellent performance.

Abstract translation: 在本发明的方法中，在自对准硅化物工艺中，在第二热处理之前，将掺杂剂注入位于从中间高度的NixSi层到其前面的区域中，或者在形成NixSi层之前 位于从NiSi层的预定厚度的一半的深度到位于NiSi层的预定前方的深度的硅层的范围内。 在第二热处理期间允许掺杂剂与NixSi层一起加热以形成Si / NiSi 2 / NiSi界面，其可以降低SBH并提高串联电阻以获得具有优异性能的半导体器件。

公开(公告)号：US20110235260A1

公开(公告)日：2011-09-29

申请号：US13158546

申请日：2011-06-13

Applicant: Jiunn-Chung Lee ,  Chien-Chung Huang

Inventor： Jiunn-Chung Lee ,  Chien-Chung Huang

IPC: G06F1/16 ,  H05K7/00

CPC classification number: G11C5/00 ,  G11C5/04 ,  H05K1/181 ,  H05K2201/09254 ,  H05K2201/10159 ,  H05K2201/10189 ,  Y02P70/611

Abstract: A dynamic radon access memory (DRAM) module includes a printed circuit board, a number of DRAM units, a number of flash memory units, a number connecting pins and an interface controller. The DRAM units and the flash memory units are distributed on the printed circuit board. The connecting pins are formed at an edge of the printed circuit board. The interface controller is electrically connected to the flash memory units and a portion of the connecting pins, wherein each of the interface controller provides at least one serial interface between the flash memory units and the portion of connecting pins thereby enabling data transmission through the portion of connecting pins in at least one serial mode. The flash memory units integrally constitute a flash disk drive in the DRAM module. Therefore, frequently installation and uninstallation of the flash memory drive can be avoided. A motherboard assembly including the aforementioned DRAM module can be developed.

Abstract translation: 动态氡存取存储器（DRAM）模块包括印刷电路板，多个DRAM单元，多个闪存单元，数字连接引脚和接口控制器。 DRAM单元和闪存单元分布在印刷电路板上。 连接销形成在印刷电路板的边缘。 接口控制器电连接到闪存单元和连接引脚的一部分，其中每个接口控制器在闪存单元和连接引脚的部分之间提供至少一个串行接口，从而使数据可以通过 在至少一个串行模式下连接引脚。 闪存单元一体地构成DRAM模块中的闪存盘驱动器。 因此，可以避免闪存驱动器的频繁安装和卸载。 可以开发包括上述DRAM模块的主板组件。

公开(公告)号：US07858421B2

公开(公告)日：2010-12-28

申请号：US12819229

申请日：2010-06-21

Applicant: Neng-Kuo Chen ,  Chien-Chung Huang

Inventor： Neng-Kuo Chen ,  Chien-Chung Huang

IPC: H01L21/00 ,  H01L29/82

CPC classification number: H01L21/823807 ,  H01L29/665 ,  H01L29/7843

Abstract: A method of forming a metal-oxide-semiconductor (MOS) transistor device is disclosed. A semiconductor substrate is prepared first, and the semiconductor substrate has agate structure, a source region and a drain region. Subsequently, a stress buffer layer is formed on the semiconductor substrate, and covers the gate structure, the source region and the drain region. Thereafter, a stressed cap layer is formed on the stress buffer layer, and a tensile stress value of the stressed cap layer is higher than a tensile stress value of the stress buffer layer. Since the stress buffer layer can prevent the stressed cap layer from breaking, the MOS transistor device can be covered by a stressed cap layer having an extremely high tensile stress value in the present invention.

Abstract translation: 公开了一种形成金属氧化物半导体（MOS）晶体管器件的方法。 首先制备半导体衬底，并且半导体衬底具有玛瑙结构，源极区和漏极区。 接着，在半导体基板上形成应力缓冲层，覆盖栅极结构，源极区域和漏极区域。 此后，在应力缓冲层上形成应力覆盖层，并且应力覆盖层的拉伸应力值高于应力缓冲层的拉伸应力值。 由于应力缓冲层可以防止应力覆盖层破裂，所以在本发明中，MOS晶体管器件可以被具有非常高的拉伸应力值的应力覆盖层覆盖。

公开(公告)号：US07645712B2

公开(公告)日：2010-01-12

申请号：US12345670

申请日：2008-12-30

Applicant: Neng-Kuo Chen ,  Teng-Chun Tsai ,  Chien-Chung Huang

Inventor： Neng-Kuo Chen ,  Teng-Chun Tsai ,  Chien-Chung Huang

IPC: H01L21/469 ,  H01L21/338

CPC classification number: H01L21/76801 ,  H01L21/76837 ,  H01L29/78

Abstract: A substrate having at least two metal oxide semiconductor devices of a same conductive type and a gap formed between the two devices is provided. A first stress layer is formed over the substrate to cover the metal-oxide semiconductor devices and the substrate, filling the gap. An etching back process is then performed to remove a portion of the stress material layer inside the gap. A second stress layer and a dielectric layer are sequentially formed on the first stress layer. The first stress layer and the second stress layer provide a same type of stress. A portion of the second stress layer is removed to form a contact opening. A second conductive layer is filled into the contact opening to form a contact.

Abstract translation: 提供了具有至少两个相同导电类型的金属氧化物半导体器件和在两个器件之间形成的间隙的衬底。 第一应力层形成在衬底上以覆盖金属氧化物半导体器件和衬底，填补间隙。 然后执行回蚀处理以去除间隙内部的应力材料层的一部分。 第一应力层和电介质层依次形成在第一应力层上。 第一应力层和第二应力层提供相同类型的应力。 去除第二应力层的一部分以形成接触开口。 将第二导电层填充到接触开口中以形成接触。

公开(公告)号：US20090061201A1

公开(公告)日：2009-03-05

申请号：US11850466

申请日：2007-09-05

Applicant: Mei-Ling Chen ,  Su-Jen Sung ,  Chien-Chung Huang

Inventor： Mei-Ling Chen ,  Su-Jen Sung ,  Chien-Chung Huang

IPC: C23C14/54 ,  B32B3/26

CPC classification number: C23C16/401 ,  C23C16/45557 ,  C23C16/46 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/02362 ,  H01L21/31695 ,  Y10T428/249953

Abstract: A fabrication method of an ultra low-k dielectric layer is provided. A deposition process is performed, under the control of a temperature varying program or a pressure varying program, by reacting a dielectric matrix to form porous low-k dielectric layers with a gradient density on a barrier layer over a substrate.

Abstract translation: 提供了一种超低k电介质层的制造方法。 在温度变化程序或压力变化程序的控制下，通过使介电基质反应以在衬底上的阻挡层上形成具有梯度密度的多孔低k电介质层来进行沉积工艺。

公开(公告)号：US07496464B2

公开(公告)日：2009-02-24

申请号：US11277040

申请日：2006-03-21

Applicant: Chien-Chung Huang ,  Yuan-Liang Cheng ,  Tung-Hao Huang ,  You-Min Yeh ,  Chung-Yu Chang

Inventor： Chien-Chung Huang ,  Yuan-Liang Cheng ,  Tung-Hao Huang ,  You-Min Yeh ,  Chung-Yu Chang

IPC: G01R27/28 ,  G06F19/00

CPC classification number: G05B23/0256

Abstract: A validation system includes: a source agent for storing a plurality of test patterns; a drain agent for performing a validation operation according to a test result; and a device under test (DUT). The device under test includes: a first interface electrically connected to the source agent for communicating with the source agent and receiving the test patterns outputted from the source agent; a target system electrically connected to the first interface for processing the test patterns to generate a plurality of test results; and a second interface electrically connected to the target system and the drain agent for communicating with the drain agent and transferring the plurality of test results to the drain agent.

Abstract translation: 验证系统包括：用于存储多个测试模式的源代理; 用于根据测试结果执行验证操作的排水剂; 和被测器件（DUT）。 被测设备包括：电源连接到源代理以与源代理通信并接收从源代理输出的测试模式的第一接口; 电连接到第一接口的目标系统，用于处理测试图案以产生多个测试结果; 以及电连接到所述目标系统和所述排水剂的第二界面，用于与所述排水剂连通并将所述多个测试结果传送到所述排水剂。

公开(公告)号：US20080293194A1

公开(公告)日：2008-11-27

申请号：US11752940

申请日：2007-05-24

Applicant: Neng-Kuo Chen ,  Chien-Chung Huang ,  Jei-Ming Chen

Inventor： Neng-Kuo Chen ,  Chien-Chung Huang ,  Jei-Ming Chen

IPC: H01L21/8238 ,  H01L21/336

CPC classification number: H01L21/2652 ,  H01L21/2658 ,  H01L21/823807 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

Abstract: A method is disclosed to make a strained-silicon PMOS or CMOS transistor, in which, a compressive stress film is formed by reacting a silane having at least one substituent selected from the group consisting of hydrocarbyl, hydrocarboxy, carbonyl, formyl, carboxylic group, ester group, and halo group and ammonia, or a conventional compressive stress film is implanted with fluorine atoms, oxygen atoms, or carbon atoms, so as to improve the properties of negative bias temperature instability (NBTI).

Abstract translation: 公开了制造应变硅PMOS或CMOS晶体管的方法，其中通过使具有至少一个选自烃基，烃羧基，羰基，甲酰基，羧基的取代基的硅烷反应形成压应力膜， 酯基，卤代基和氨，或者常规的压应力膜注入氟原子，氧原子或碳原子，以提高负偏压温度不稳定性（NBTI）的性质。

公开(公告)号：US20080142902A1

公开(公告)日：2008-06-19

申请号：US12013482

申请日：2008-01-14

Applicant: Neng-Kuo Chen ,  Teng-Chun Tsai ,  Chien-Chung Huang ,  Tsai-Fu Chen ,  Wen-Han Hung

Inventor： Neng-Kuo Chen ,  Teng-Chun Tsai ,  Chien-Chung Huang ,  Tsai-Fu Chen ,  Wen-Han Hung

IPC: H01L29/78

CPC classification number: H01L21/0217 ,  C23C16/345 ,  C23C16/56 ,  H01L21/02274 ,  H01L21/02348 ,  H01L21/3185 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

Abstract: A metal-oxide-semiconductor (MOS) transistor device is disclosed. The MOS transistor device comprises a semiconductor substrate; a gate structure on the semiconductor substrate; source/drain regions on the semiconductor substrate adjacent to the gate structure; an ultra-high tensile-stressed nitride film having a hydrogen concentration of less than 1E22 atoms/cm3 covering the gate structure and the source/drain regions; and an inter-layer dielectric (ILD) film over the ultra-high tensile-stressed nitride film.

Abstract translation: 公开了一种金属氧化物半导体（MOS）晶体管器件。 MOS晶体管器件包括半导体衬底; 半导体衬底上的栅极结构; 与栅极结构相邻的半导体衬底上的源/漏区; 具有覆盖栅极结构和源极/漏极区域的小于1E22原子/ cm 3的氢浓度的超高拉伸应力氮化物膜; 和超高拉伸应力氮化物膜上的层间电介质（ILD）膜。

公开(公告)号：US20080099801A1

公开(公告)日：2008-05-01

申请号：US11552532

申请日：2006-10-25

Applicant: Kun-Hsien Lee ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Shyh-Fann Ting ,  Li-Shian Jeng ,  Tzyy-Ming Cheng ,  Neng-Kuo Chen ,  Shao-Ta Hsu ,  Teng-Chun Tsai ,  Chien-Chung Huang

Inventor： Kun-Hsien Lee ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Shyh-Fann Ting ,  Li-Shian Jeng ,  Tzyy-Ming Cheng ,  Neng-Kuo Chen ,  Shao-Ta Hsu ,  Teng-Chun Tsai ,  Chien-Chung Huang

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/00 ,  H01L21/8234 ,  H01L21/336

CPC classification number: H01L21/823807 ,  H01L21/823835 ,  H01L21/82385 ,  H01L21/823864 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/7843

Abstract: A method of manufacturing a MOS transistor device. First, a semiconductor substrate having a gate structure is prepared. The gate structure has two sidewalls and a liner on the sidewalls. Subsequently, a stressed cap layer is formed on the semiconductor substrate, and covers the gate structure and the liner. Next, an activating process is performed. Furthermore, the stressed cap layer is etched to be a salicide block. Afterward, a salicide process is performed to form a silicide layer on the regions that are not covered by the stressed cap layer.

Abstract translation: 一种制造MOS晶体管器件的方法。 首先，准备具有栅极结构的半导体衬底。 栅极结构在侧壁上具有两个侧壁和衬垫。 随后，在半导体衬底上形成应力覆盖层，并覆盖栅极结构和衬垫。 接下来，执行激活处理。 此外，将应力覆盖层蚀刻成为自对准硅化物块。 之后，进行自对准处理以在未被应力覆盖层覆盖的区域上形成硅化物层。