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    Biodegradable Composition
    1.
    发明申请
    Biodegradable Composition 有权

    公开(公告)号：US20210347985A1

    公开(公告)日：2021-11-11

    申请号：US17250790

    申请日：2018-09-07

    Applicant: Chien-Chung HUANG

    Inventor： Chien-Chung Huang ,  Yeng-Fong Shih

    IPC: C08L67/04 ,  C08L67/02 ,  C08K7/02

    Abstract: Disclosed is a biodegradable composition, including: 5 to 90 percent by weight of polylactic acid (PLA), 5 to 80 percent by weight of plant fiber, and 5 to 70 percent by weight of maleic anhydride-grafted polybutylene succinate (PBS-g-MA), acrylic acid-grafted polybutylene succinate (PBS-g-AA), or silane coupling agent-grafted polybutylene succinate (PBS-g-Silane). The article manufactured therefrom is not only biodegradable but also has an enhanced heat deformation temperature, impact resistance and tensile strength. Further, by so limiting the proportion of each component, compatibility between the components may be increased and crystallization of polylactic acid may be facilitated.

    Method for clearing native oxide
    2.
    发明授权
    Method for clearing native oxide 有权
    清除天然氧化物的方法

    公开(公告)号：US08642477B2

    公开(公告)日：2014-02-04

    申请号：US12129978

    申请日：2008-05-30

    Applicant: Yen-Chu Chen ,  Teng-Chun Tsai ,  Chien-Chung Huang ,  Keng-Jen Liu

    Inventor： Yen-Chu Chen ,  Teng-Chun Tsai ,  Chien-Chung Huang ,  Keng-Jen Liu

    IPC: H01L21/302 ,  C23F1/00

    CPC classification number: H01L21/3065 ,  H01L21/02057 ,  H01L21/02063

    Abstract: A method for clearing native oxide is described. A substrate is provided, including an exposed portion whereon a native oxide layer has been formed. A clearing process is performed to the substrate using nitrogen trifluoride (NF3) and ammonia (NH3) as a reactant gas, wherein the volumetric flow rate of NF3 is greater than that of NH3.

    Abstract translation: 描述了清除天然氧化物的方法。 提供了一种衬底，包括其中形成有自然氧化物层的暴露部分。 使用三氟化氮（NF 3）和氨（NH 3）作为反应气体对基板进行清除处理，其中NF 3的体积流量大于NH 3的体积流量。

    DAMASCENE STRUCTURE
    3.
    发明申请
    DAMASCENE STRUCTURE 有权
    大田结构

    公开(公告)号：US20120146225A1

    公开(公告)日：2012-06-14

    申请号：US13397833

    申请日：2012-02-16

    Applicant: Yu-Ru YANG ,  Chien-Chung Huang

    Inventor： Yu-Ru YANG ,  Chien-Chung Huang

    IPC: H01L23/532

    CPC classification number: H01L21/2855 ,  H01L21/76844 ,  H01L21/76846

    Abstract: A damascene structure includes a conductive layer, a first dielectric layer, a first barrier metal layer, a barrier layer, and a second barrier metal layer sequentially formed on the conductive layer. The first dielectric layer having a via therein. The barrier layer is comprised of a material different with that of the first barrier metal layer. A bottom of the barrier layer disposed on the via bottom is not punched through. The accomplished barrier layers will have lower resistivity on the via bottom in the first dielectric layer and they are capable of preventing copper atoms from diffusing into the dielectric layer.

    Abstract translation: 镶嵌结构包括依次形成在导电层上的导电层，第一介电层，第一阻挡金属层，阻挡层和第二阻挡金属层。 第一电介质层中具有通孔。 阻挡层由与第一阻挡金属层不同的材料构成。 设置在通孔底部上的阻挡层的底部不穿孔。 完成的阻挡层在第一介电层中的通孔底部具有较低的电阻率，并且它们能够防止铜原子扩散到电介质层中。

    Semiconductor device and method of making the same
    4.
    发明授权
    Semiconductor device and method of making the same 有权
    半导体器件及其制造方法

    公开(公告)号：US08163607B2

    公开(公告)日：2012-04-24

    申请号：US12769649

    申请日：2010-04-29

    Applicant: Yi-Wei Chen ,  Nien-Ting Ho ,  Kuo-Chih Lai ,  Chien-Chung Huang

    Inventor： Yi-Wei Chen ,  Nien-Ting Ho ,  Kuo-Chih Lai ,  Chien-Chung Huang

    IPC: H01L21/8283

    CPC classification number: H01L29/665 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/28518 ,  H01L21/823443 ,  H01L21/823835 ,  H01L29/6659 ,  H01L29/7833

    Abstract: In a method of the present invention during a salicide process, before a second thermal process, a dopant is implanted at a place located in a region ranging from a NixSi layer at meddle height down to a front thereof, or before formation of the NixSi layer, located in a region ranging from a silicon layer at a depth ranging from a half of a predetermined thickness of a NiSi layer down to a depth where is a predetermined front of the NiSi layer. The dopant is allowed to be heated with the NixSi layer together during the second thermal process to form a Si/NiSi2/NiSi interface which may reduce SBH and improve series resistance to obtain a semiconductor device having an excellent performance.

    Abstract translation: 在本发明的方法中，在自对准硅化物工艺中，在第二热处理之前，将掺杂剂注入位于从中间高度的NixSi层到其前面的区域中，或者在形成NixSi层之前 位于从NiSi层的预定厚度的一半的深度到位于NiSi层的预定前方的深度的硅层的范围内。 在第二热处理期间允许掺杂剂与NixSi层一起加热以形成Si / NiSi 2 / NiSi界面，其可以降低SBH并提高串联电阻以获得具有优异性能的半导体器件。

    METHOD OF FORMING METAL-OXIDE-SEMICONDUCTOR TRANSISTOR
    6.
    发明申请
    METHOD OF FORMING METAL-OXIDE-SEMICONDUCTOR TRANSISTOR 有权
    形成金属氧化物半导体晶体管的方法

    公开(公告)号：US20100261323A1

    公开(公告)日：2010-10-14

    申请号：US12819229

    申请日：2010-06-21

    Applicant: Neng-Kuo Chen ,  Chien-Chung Huang

    Inventor： Neng-Kuo Chen ,  Chien-Chung Huang

    IPC: H01L21/8238 ,  H01L21/316

    CPC classification number: H01L21/823807 ,  H01L29/665 ,  H01L29/7843

    Abstract: A method of forming a metal-oxide-semiconductor (MOS) transistor device is disclosed. A semiconductor substrate is prepared first, and the semiconductor substrate has agate structure, a source region and a drain region. Subsequently, a stress buffer layer is formed on the semiconductor substrate, and covers the gate structure, the source region and the drain region. Thereafter, a stressed cap layer is formed on the stress buffer layer, and a tensile stress value of the stressed cap layer is higher than a tensile stress value of the stress buffer layer. Since the stress buffer layer can prevent the stressed cap layer from breaking, the MOS transistor device can be covered by a stressed cap layer having an extremely high tensile stress value in the present invention.

    Abstract translation: 公开了一种形成金属氧化物半导体（MOS）晶体管器件的方法。 首先制备半导体衬底，并且半导体衬底具有玛瑙结构，源极区和漏极区。 接着，在半导体基板上形成应力缓冲层，覆盖栅极结构，源极区域和漏极区域。 此后，在应力缓冲层上形成应力覆盖层，并且应力覆盖层的拉伸应力值高于应力缓冲层的拉伸应力值。 由于应力缓冲层可以防止应力覆盖层破裂，所以在本发明中，MOS晶体管器件可以被具有非常高的拉伸应力值的应力覆盖层覆盖。

    Metal-oxide-semiconductor transistor and method of forming the same
    7.
    发明授权
    Metal-oxide-semiconductor transistor and method of forming the same 有权
    金属氧化物半导体晶体管及其形成方法

    公开(公告)号：US07777284B2

    公开(公告)日：2010-08-17

    申请号：US11754362

    申请日：2007-05-28

    Applicant: Neng-Kuo Chen ,  Chien-Chung Huang

    Inventor： Neng-Kuo Chen ,  Chien-Chung Huang

    IPC: H01L29/82 ,  H01L21/00

    CPC classification number: H01L21/823807 ,  H01L29/665 ,  H01L29/7843

    Abstract: A method of forming a metal-oxide-semiconductor (MOS) transistor device is disclosed. A semiconductor substrate is prepared first, and the semiconductor substrate has a gate structure, a source region and a drain region. Subsequently, a stress buffer layer is formed on the semiconductor substrate, and covers the gate structure, the source region and the drain region. Thereafter, a stressed cap layer is formed on the stress buffer layer, and a tensile stress value of the stressed cap layer is higher than a tensile stress value of the stress buffer layer. Since the stress buffer layer can prevent the stressed cap layer from breaking, the MOS transistor device can be covered by a stressed cap layer having an extremely high tensile stress value in the present invention.

    Abstract translation: 公开了一种形成金属氧化物半导体（MOS）晶体管器件的方法。 首先制备半导体衬底，并且半导体衬底具有栅极结构，源极区和漏极区。 接着，在半导体基板上形成应力缓冲层，覆盖栅极结构，源极区域和漏极区域。 此后，在应力缓冲层上形成应力覆盖层，并且应力覆盖层的拉伸应力值高于应力缓冲层的拉伸应力值。 由于应力缓冲层可以防止应力覆盖层破裂，所以在本发明中，MOS晶体管器件可以被具有非常高的拉伸应力值的应力覆盖层覆盖。

    DRAM MODULE WITH SOLID STATE DISK
    10.
    发明申请
    DRAM MODULE WITH SOLID STATE DISK 有权
    具有固态盘的DRAM模块

    公开(公告)号：US20090257184A1

    公开(公告)日：2009-10-15

    申请号：US12100023

    申请日：2008-04-09

    Applicant: Jiunn-Chung LEE ,  Chien-Chung Huang

    Inventor： Jiunn-Chung LEE ,  Chien-Chung Huang

    IPC: H05K7/00 ,  H05K1/11 ,  H05K1/14

    CPC classification number: H05K1/181 ,  G11C5/00 ,  H05K2201/09254 ,  H05K2201/10159 ,  H05K2201/10189 ,  Y02P70/611

    Abstract: A dynamic radon access memory (DRAM) module includes a printed circuit board, a number of DRAM units, a number of flash memory units, a number connecting pins and an interface controller. The DRAM units and the flash memory units are distributed on the printed circuit board. The connecting pins are formed at an edge of the printed circuit board. The interface controller is electrically connected to the flash memory units and a portion of the connecting pins, wherein each of the interface controller provides at least one serial interface between the flash memory units and the portion of connecting pins thereby enabling data transmission through the portion of connecting pins in at least one serial mode. The flash memory units integrally constitute a flash disk drive in the DRAM module. Therefore, frequently installation and uninstallation of the flash memory drive can be avoided. A motherboard assembly including the aforementioned DRAM module can be developed.

    Abstract translation: 动态氡存取存储器（DRAM）模块包括印刷电路板，多个DRAM单元，多个闪存单元，数字连接引脚和接口控制器。 DRAM单元和闪存单元分布在印刷电路板上。 连接销形成在印刷电路板的边缘。 接口控制器电连接到闪存单元和连接引脚的一部分，其中每个接口控制器在闪存单元和连接引脚的部分之间提供至少一个串行接口，从而使数据可以通过 在至少一个串行模式下连接引脚。 闪存单元一体地构成DRAM模块中的闪存盘驱动器。 因此，可以避免闪存驱动器的频繁安装和卸载。 可以开发包括上述DRAM模块的主板组件。

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